ADBMS1818ASWZ-RL

Analog Devices · Battery Management · LQFP-64-EP(10x10)

ADBMS1818ASWZ-RL from Analog Devices, in a LQFP-64-EP(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	V+	power_in	Positive supply pin; absolute maximum V+ to V- is 112.5 V.
2	C0	input	Cell input C0 (bottom of the cell stack); absolute maximum -0.3 V to +6 V relative to V-.
3	S1	bidirectional	Balance input/output 1; internal N-channel MOSFET connected between S1 and C0 for discharging the cell.
4	C1	input	Cell input C1.
5	S2	bidirectional	Balance input/output 2; internal N-channel MOSFET connected between S2 and C1 for discharging the cell.
6	C2	input	Cell input C2.
7	S3	bidirectional	Balance input/output 3; internal N-channel MOSFET connected between S3 and C2 for discharging the cell.
8	C3	input	Cell input C3.
9	S4	bidirectional	Balance input/output 4; internal N-channel MOSFET connected between S4 and C3 for discharging the cell.
10	C4	input	Cell input C4.
11	S5	bidirectional	Balance input/output 5; internal N-channel MOSFET connected between S5 and C4 for discharging the cell.
12	C5	input	Cell input C5.
13	S6	bidirectional	Balance input/output 6; internal N-channel MOSFET connected between S6 and C5 for discharging the cell.
14	C6	input	Cell input C6.
15	S7	bidirectional	Balance input/output 7; internal N-channel MOSFET connected between S7 and C6 for discharging the cell.
16	C7	input	Cell input C7.
17	S8	bidirectional	Balance input/output 8; internal N-channel MOSFET connected between S8 and C7 for discharging the cell.
18	C8	input	Cell input C8.
19	S9	bidirectional	Balance input/output 9; internal N-channel MOSFET connected between S9 and C8 for discharging the cell.
20	C9	input	Cell input C9.
21	S10	bidirectional	Balance input/output 10; internal N-channel MOSFET connected between S10 and C9 for discharging the cell.
22	C10	input	Cell input C10.
23	S11	bidirectional	Balance input/output 11; internal N-channel MOSFET connected between S11 and C10 for discharging the cell.
24	C11	input	Cell input C11.
25	S12	bidirectional	Balance input/output 12; internal N-channel MOSFET connected between S12 and C11 for discharging the cell.
26	C12	input	Cell input C12; V+ must stay within 50 V of C12.
27	S13	bidirectional	Balance input/output 13; internal N-channel MOSFET connected between S13 and C12 for discharging the cell.
28	C13	input	Cell input C13.
29	S14	bidirectional	Balance input/output 14; internal N-channel MOSFET connected between S14 and C13 for discharging the cell.
30	C14	input	Cell input C14.
31	S15	bidirectional	Balance input/output 15; internal N-channel MOSFET connected between S15 and C14 for discharging the cell.
32	C15	input	Cell input C15.
33	S16	bidirectional	Balance input/output 16; internal N-channel MOSFET connected between S16 and C15 for discharging the cell.
34	C16	input	Cell input C16.
35	S17	bidirectional	Balance input/output 17; internal N-channel MOSFET connected between S17 and C16 for discharging the cell.
36	C17	input	Cell input C17.
37	S18	bidirectional	Balance input/output 18; internal N-channel MOSFET connected between S18 and C17 for discharging the cell.
38	C18	input	Cell input C18 (top cell); absolute maximum -0.3 V to MIN(V+ + 5.5 V, 112.5 V) relative to V-.
39	GPIO1	bidirectional	General purpose I/O usable as digital input/output or analog input with measurement range V- to 5 V.
40	GPIO2	bidirectional	General purpose I/O usable as digital input/output or analog input with measurement range V- to 5 V.
41	GPIO3	bidirectional	General purpose I/O (digital in/out or analog input, V- to 5 V) that can also be used as an I2C or SPI port.
42	GPIO4	bidirectional	General purpose I/O (digital in/out or analog input, V- to 5 V) that can also be used as an I2C or SPI port.
43	GPIO5	bidirectional	General purpose I/O (digital in/out or analog input, V- to 5 V) that can also be used as an I2C or SPI port.
44	GPIO6	bidirectional	General purpose I/O usable as digital input/output or analog input with measurement range V- to 5 V.
45	GPIO7	bidirectional	General purpose I/O usable as digital input/output or analog input with measurement range V- to 5 V.
46	GPIO8	bidirectional	General purpose I/O usable as digital input/output or analog input with measurement range V- to 5 V.
47	GPIO9	bidirectional	General purpose I/O usable as digital input/output or analog input with measurement range V- to 5 V.
48	VREG	power_in	5 V regulator pin; bypass with an external 1 µF capacitor.
49	DRIVE	output	Connect the base of an NPN transistor here, with its collector to V+ and emitter to VREG; absolute maximum -0.3 V to +7 V.
50	VREF2	output	Buffered 2nd reference voltage for driving multiple 10 kΩ thermistors; bypass with an external 1 µF capacitor.
51	VREF1	output	ADC reference voltage; bypass with an external 1 µF capacitor, no dc loads allowed.
52	DTEN	input	Discharge timer enable; connect to VREG to enable the discharge timer.
53	SDI	input	4-wire SPI serial data in digital input (not connected in isoSPI mode).
54	SDO	output	4-wire SPI serial data out, open-drain NMOS output requiring a 5 kΩ pull-up resistor (not connected in isoSPI mode).
55	ISOMD	input	Serial interface mode select: connect to VREG for 2-wire isoSPI mode, or to V- for 4-wire SPI mode.
56	WDT	output	Open-drain NMOS watchdog timer output; can be left disconnected or tied via 1 MΩ to VREG, goes high impedance if no valid command is received within 2 seconds.
57	IBIAS	passive	Isolated interface current bias; tie to V- through a resistor divider, pin is at 2 V when isoSPI is enabled and output drive current is 20 times the IB sourced.
58	ICMP	input	Isolated interface comparator threshold set; tie to the resistor divider between IBIAS and V-, comparator thresholds are half the ICMP voltage.
59	V-	power_in	Negative supply pin; the V- pins must be shorted together externally to the IC.
60	V-	power_in	Negative supply pin; the V- pins must be shorted together externally to the IC.
61	CSB/IMA	bidirectional	Active-low chip select (4-wire SPI) or IMA, negative of the differential isoSPI port A pair.
62	SCK/IPA	bidirectional	Serial clock input (4-wire SPI) or IPA, positive of the differential isoSPI port A pair.
63	IMB	bidirectional	Isolated 2-wire serial interface port B, negative of differential input/output pair; output drive current limits are 30 mA absolute maximum.
64	IPB	bidirectional	Isolated 2-wire serial interface port B, positive of differential input/output pair; output drive current limits are 30 mA absolute maximum.
65	EPAD	power_in	Exposed pad (V-); must be soldered to the PCB and connected to the V- plane for thermal management.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LQFP-64-EP(10x10)
Category	Power Management (PMIC)
Pins	65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
TME normal mode, C(n) to C(n-1), GPIO(n) to V- = 0		-0.2		0.2	mV	Normal mode; C(n) to C(n-1), GPIO(n) to V- = 0	4
TME normal mode, C(n) to C(n-1) = 2.0		-2.6		2.6	mV	Normal mode; C(n) to C(n-1) = 2.0	4
TME normal mode, GPIO(n) to V- = 2.0, full temp range		-2.8		2.8	mV	Normal mode; C(n) to C(n-1), GPIO(n) to V- = 2.0, apply over the full specified temperature range	4
TME normal mode, C(n) to C(n-1) = 3.3		-3		3	mV	Normal mode; C(n) to C(n-1) = 3.3	4
TME normal mode, GPIO(n) to V- = 3.3, full temp range		-4		4	mV	Normal mode; C(n) to C(n-1), GPIO(n) to V- = 3.3, apply over the full specified temperature range	4
TME normal mode, C(n) to C(n-1) = 4.2		-3.8		3.8	mV	Normal mode; C(n) to C(n-1) = 4.2	4
TME normal mode, GPIO(n) to V- = 4.2, full temp range		-4.8		4.8	mV	Normal mode; C(n) to C(n-1), GPIO(n) to V- = 4.2, apply over the full specified temperature range	4
TME normal mode, GPIO(n) to V- = 5.0		-1		1	mV	Normal mode; C(n) to C(n-1), GPIO(n) to V- = 5.0	4
TME normal mode, sum of all cells		-0.35		0.35	%	Normal mode; sum of all cells, apply over the full specified temperature range (printed +/-0.05 typ, +/-0.35 max)	4
TME normal mode, internal temperature		-5		5	°C	Normal mode; internal temperature, T = maximum specified temperature	4
TME normal mode, VREG pin	VREG	-1	-0.15	0	%	Normal mode; VREG pin, apply over the full specified temperature range	4
TME normal mode, VREF2 pin	VREF2	-0.05	0.05	0.2	%	Normal mode; VREF2 pin, apply over the full specified temperature range	4
TME normal mode, digital supply VREGD	VREGD	-0.5	0.5	1.5	%	Normal mode; digital supply voltage VREGD, apply over the full specified temperature range	4
TME filtered mode, C(n) to C(n-1), GPIO(n) to V- = 0		-0.1		0.1	mV	Filtered mode; C(n) to C(n-1), GPIO(n) to V- = 0	4
TME filtered mode, C(n) to C(n-1) = 2.0		-1.6		1.6	mV	Filtered mode; C(n) to C(n-1) = 2.0	4
TME filtered mode, GPIO(n) to V- = 2.0, full temp range		-1.8		1.8	mV	Filtered mode; C(n) to C(n-1), GPIO(n) to V- = 2.0, apply over the full specified temperature range	4
TME filtered mode, C(n) to C(n-1) = 3.3		-2.2		2.2	mV	Filtered mode; C(n) to C(n-1) = 3.3	4
TME filtered mode, GPIO(n) to V- = 3.3, full temp range		-3		3	mV	Filtered mode; C(n) to C(n-1), GPIO(n) to V- = 3.3, apply over the full specified temperature range	4
TME filtered mode, C(n) to C(n-1) = 4.2		-2.8		2.8	mV	Filtered mode; C(n) to C(n-1) = 4.2	4
TME filtered mode, GPIO(n) to V- = 4.2, full temp range		-3.8		3.8	mV	Filtered mode; C(n) to C(n-1), GPIO(n) to V- = 4.2, apply over the full specified temperature range	4
TME filtered mode, GPIO(n) to V- = 5.0		-1		1	mV	Filtered mode; C(n) to C(n-1), GPIO(n) to V- = 5.0	4
TME filtered mode, sum of all cells		-0.35		0.35	%	Filtered mode; sum of all cells, apply over the full specified temperature range (printed +/-0.05 typ, +/-0.35 max)	4
TME filtered mode, internal temperature		-5		5	°C	Filtered mode; internal temperature, T = maximum specified temperature	4
TME filtered mode, VREG pin	VREG	-1	-0.15	0	%	Filtered mode; VREG pin, apply over the full specified temperature range	4
TME filtered mode, VREF2 pin	VREF2	-0.05	0.05	0.2	%	Filtered mode; VREF2 pin, apply over the full specified temperature range	4
TME filtered mode, digital supply VREGD	VREGD	-0.5	0.8	1.5	%	Filtered mode; digital supply voltage VREGD, apply over the full specified temperature range	4
1st Reference Voltage	VREF1	3	3.15	3.3	V	VREF1 pin, no load, apply over the full specified temperature range	5
2nd Reference Voltage	VREF2	2.993	3	3.007	V	VREF2 pin, no load, apply over the full specified temperature range	5
2nd Reference Voltage with 5 kΩ load	VREF2	2.992	3	3.008	V	VREF2 pin, 5 kΩ load to V-, apply over the full specified temperature range	5
V+ Supply Current, sleep	IVP	3		5	µA	State: core = sleep, isoSPI = idle, VREG = 5 V	5
V+ Supply Current, standby	IVP	9	14	22	µA	State: core = standby	5
V+ Supply Current, REFUP	IVP	0.4	0.55	0.8	mA	State: core = REFUP	5
V+ Supply Current, measure	IVP	0.65	0.95	1.35	mA	State: core = measure	5
VREG Supply Current, standby	IREG(CORE)	10	35	60	µA	State: core = standby	6
VREG Supply Current, REFUP	IREG(CORE)	0.4	0.9	1.4	mA	State: core = REFUP	6
VREG Supply Current, measure	IREG(CORE)	14	15	16	mA	State: core = measure	6
V+ Supply Voltage	V+	16	60	90	V	TME specifications met, apply over the full specified temperature range	6
VREG Supply Voltage	VREG	4.5	5	5.5	V	TME supply rejection < 1 mV/V, apply over the full specified temperature range	6
DRIVE Output Voltage	DRIVE	5.4	5.7	5.9	V	Sourcing 1 µA	6
Digital Supply Voltage	VREGD	2.7	3	3.6	V	Apply over the full specified temperature range	6
Discharge Switch On Resistance		4		10	Ω	VCELL = 3.6 V, apply over the full specified temperature range	6
Data Return Delay	tRTN	325	375	425	ns	Apply over the full specified temperature range	10
Data Daisy-Chain Delay	tDSY(D)	200	250	300	ns	Apply over the full specified temperature range	10
Input Voltage (Relative to V-), C0	C0	-0.3		6	V	Relative to V-	11
Input Voltage (Relative to V-), C18	C18	-0.3			V	Relative to V-; max = MIN(V+ + 5.5 V, 112.5 V)	11
Input Voltage (Relative to V-), C(n), S(n)	C(n), S(n)	-0.3			V	Relative to V-; max = MIN(8 × n, 112.5 V)	11
Input Voltage (Relative to V-), IPA, IMA, IPB, IMB	IPA, IMA, IPB, IMB	-0.3			V	Relative to V-; max = VREG + 0.3 V, ≤ 6 V	11
Input Voltage (Relative to V-), DRIVE	DRIVE	-0.3		7	V	Relative to V-	11
Input Voltage (Relative to V-), all other pins		-0.3		6	V	Relative to V-; all other pins	11
Voltage Between Inputs, C(n) to C(n-1) and S(n) to C(n-1)		-0.3		8	V	C(n) to C(n-1) and S(n) to C(n-1)	11
Voltage Between Inputs, C18 to C15 ... C3 to C0		-0.3		21	V	C18 to C15, C15 to C12, C12 to C9, C9 to C6, C6 to C3, C3 to C0	11
Total Supply Voltage, V+ to V-	V+ to V-			112.5	V		11
Supply Voltage relative to C12, V+ to C12	V+ to C12			50	V	Relative to C12	11
Current In and Out of Pins, all except VREG, IPA, IMA, IPB, IMB, C(n), S(n)				10	mA	All pins except VREG, IPA, IMA, IPB, IMB, C(n), and S(n)	11
Current In and Out of Pins, IPA, IMA, IPB, IMB	IPA, IMA, IPB, IMB			30	mA	IPA, IMA, IPB, and IMB	11
Specified Junction Temperature Range	TJ	-40		85	°C	Specified junction temperature range	11
Junction Temperature (TJMAX)	TJMAX			150	°C		11
Storage Temperature Range		-65		150	°C		11
Thermal Resistance, junction to ambient (θJA)	θJA		17		°C/W	SW-64-2 (64-lead LQFP_EP); natural convection, one-cubic-foot sealed enclosure; board layout dependent	11
Thermal Resistance, junction to case (θJC)	θJC		2.5		°C/W	SW-64-2 (64-lead LQFP_EP)	11

CAD (KiCad official)

Symbol: ADBMS1818ASWZ-RL
Footprint: Package_QFP:LQFP-64-1EP_10x10mm_P0.5mm_EP6.5x6.5mm
3D model: LQFP-64-EP(10x10) (KiCad packages3D, STEP)
3D model files: adbms1818aswz-rl-etched.step / adbms1818aswz-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adbms1818aswz-rl.step / adbms1818aswz-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (89 pp, sha256 fdab29ebeb2e5ec7, retrieved 2026-10-17, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# ADBMS1818ASWZ-RL

**Analog Devices** · Battery Management · LQFP-64-EP(10x10)

ADBMS1818ASWZ-RL from Analog Devices, in a LQFP-64-EP(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | V+ | power_in | Positive supply pin; absolute maximum V+ to V- is 112.5 V. |
| 2 | C0 | input | Cell input C0 (bottom of the cell stack); absolute maximum -0.3 V to +6 V relative to V-. |
| 3 | S1 | bidirectional | Balance input/output 1; internal N-channel MOSFET connected between S1 and C0 for discharging the cell. |
| 4 | C1 | input | Cell input C1. |
| 5 | S2 | bidirectional | Balance input/output 2; internal N-channel MOSFET connected between S2 and C1 for discharging the cell. |
| 6 | C2 | input | Cell input C2. |
| 7 | S3 | bidirectional | Balance input/output 3; internal N-channel MOSFET connected between S3 and C2 for discharging the cell. |
| 8 | C3 | input | Cell input C3. |
| 9 | S4 | bidirectional | Balance input/output 4; internal N-channel MOSFET connected between S4 and C3 for discharging the cell. |
| 10 | C4 | input | Cell input C4. |
| 11 | S5 | bidirectional | Balance input/output 5; internal N-channel MOSFET connected between S5 and C4 for discharging the cell. |
| 12 | C5 | input | Cell input C5. |
| 13 | S6 | bidirectional | Balance input/output 6; internal N-channel MOSFET connected between S6 and C5 for discharging the cell. |
| 14 | C6 | input | Cell input C6. |
| 15 | S7 | bidirectional | Balance input/output 7; internal N-channel MOSFET connected between S7 and C6 for discharging the cell. |
| 16 | C7 | input | Cell input C7. |
| 17 | S8 | bidirectional | Balance input/output 8; internal N-channel MOSFET connected between S8 and C7 for discharging the cell. |
| 18 | C8 | input | Cell input C8. |
| 19 | S9 | bidirectional | Balance input/output 9; internal N-channel MOSFET connected between S9 and C8 for discharging the cell. |
| 20 | C9 | input | Cell input C9. |
| 21 | S10 | bidirectional | Balance input/output 10; internal N-channel MOSFET connected between S10 and C9 for discharging the cell. |
| 22 | C10 | input | Cell input C10. |
| 23 | S11 | bidirectional | Balance input/output 11; internal N-channel MOSFET connected between S11 and C10 for discharging the cell. |
| 24 | C11 | input | Cell input C11. |
| 25 | S12 | bidirectional | Balance input/output 12; internal N-channel MOSFET connected between S12 and C11 for discharging the cell. |
| 26 | C12 | input | Cell input C12; V+ must stay within 50 V of C12. |
| 27 | S13 | bidirectional | Balance input/output 13; internal N-channel MOSFET connected between S13 and C12 for discharging the cell. |
| 28 | C13 | input | Cell input C13. |
| 29 | S14 | bidirectional | Balance input/output 14; internal N-channel MOSFET connected between S14 and C13 for discharging the cell. |
| 30 | C14 | input | Cell input C14. |
| 31 | S15 | bidirectional | Balance input/output 15; internal N-channel MOSFET connected between S15 and C14 for discharging the cell. |
| 32 | C15 | input | Cell input C15. |
| 33 | S16 | bidirectional | Balance input/output 16; internal N-channel MOSFET connected between S16 and C15 for discharging the cell. |
| 34 | C16 | input | Cell input C16. |
| 35 | S17 | bidirectional | Balance input/output 17; internal N-channel MOSFET connected between S17 and C16 for discharging the cell. |
| 36 | C17 | input | Cell input C17. |
| 37 | S18 | bidirectional | Balance input/output 18; internal N-channel MOSFET connected between S18 and C17 for discharging the cell. |
| 38 | C18 | input | Cell input C18 (top cell); absolute maximum -0.3 V to MIN(V+ + 5.5 V, 112.5 V) relative to V-. |
| 39 | GPIO1 | bidirectional | General purpose I/O usable as digital input/output or analog input with measurement range V- to 5 V. |
| 40 | GPIO2 | bidirectional | General purpose I/O usable as digital input/output or analog input with measurement range V- to 5 V. |
| 41 | GPIO3 | bidirectional | General purpose I/O (digital in/out or analog input, V- to 5 V) that can also be used as an I2C or SPI port. |
| 42 | GPIO4 | bidirectional | General purpose I/O (digital in/out or analog input, V- to 5 V) that can also be used as an I2C or SPI port. |
| 43 | GPIO5 | bidirectional | General purpose I/O (digital in/out or analog input, V- to 5 V) that can also be used as an I2C or SPI port. |
| 44 | GPIO6 | bidirectional | General purpose I/O usable as digital input/output or analog input with measurement range V- to 5 V. |
| 45 | GPIO7 | bidirectional | General purpose I/O usable as digital input/output or analog input with measurement range V- to 5 V. |
| 46 | GPIO8 | bidirectional | General purpose I/O usable as digital input/output or analog input with measurement range V- to 5 V. |
| 47 | GPIO9 | bidirectional | General purpose I/O usable as digital input/output or analog input with measurement range V- to 5 V. |
| 48 | VREG | power_in | 5 V regulator pin; bypass with an external 1 µF capacitor. |
| 49 | DRIVE | output | Connect the base of an NPN transistor here, with its collector to V+ and emitter to VREG; absolute maximum -0.3 V to +7 V. |
| 50 | VREF2 | output | Buffered 2nd reference voltage for driving multiple 10 kΩ thermistors; bypass with an external 1 µF capacitor. |
| 51 | VREF1 | output | ADC reference voltage; bypass with an external 1 µF capacitor, no dc loads allowed. |
| 52 | DTEN | input | Discharge timer enable; connect to VREG to enable the discharge timer. |
| 53 | SDI | input | 4-wire SPI serial data in digital input (not connected in isoSPI mode). |
| 54 | SDO | output | 4-wire SPI serial data out, open-drain NMOS output requiring a 5 kΩ pull-up resistor (not connected in isoSPI mode). |
| 55 | ISOMD | input | Serial interface mode select: connect to VREG for 2-wire isoSPI mode, or to V- for 4-wire SPI mode. |
| 56 | WDT | output | Open-drain NMOS watchdog timer output; can be left disconnected or tied via 1 MΩ to VREG, goes high impedance if no valid command is received within 2 seconds. |
| 57 | IBIAS | passive | Isolated interface current bias; tie to V- through a resistor divider, pin is at 2 V when isoSPI is enabled and output drive current is 20 times the IB sourced. |
| 58 | ICMP | input | Isolated interface comparator threshold set; tie to the resistor divider between IBIAS and V-, comparator thresholds are half the ICMP voltage. |
| 59 | V- | power_in | Negative supply pin; the V- pins must be shorted together externally to the IC. |
| 60 | V- | power_in | Negative supply pin; the V- pins must be shorted together externally to the IC. |
| 61 | CSB/IMA | bidirectional | Active-low chip select (4-wire SPI) or IMA, negative of the differential isoSPI port A pair. |
| 62 | SCK/IPA | bidirectional | Serial clock input (4-wire SPI) or IPA, positive of the differential isoSPI port A pair. |
| 63 | IMB | bidirectional | Isolated 2-wire serial interface port B, negative of differential input/output pair; output drive current limits are 30 mA absolute maximum. |
| 64 | IPB | bidirectional | Isolated 2-wire serial interface port B, positive of differential input/output pair; output drive current limits are 30 mA absolute maximum. |
| 65 | EPAD | power_in | Exposed pad (V-); must be soldered to the PCB and connected to the V- plane for thermal management. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LQFP-64-EP(10x10) |
| Category | Power Management (PMIC) |
| Pins | 65 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| TME normal mode, C(n) to C(n-1), GPIO(n) to V- = 0 |  | -0.2 |  | 0.2 | mV | Normal mode; C(n) to C(n-1), GPIO(n) to V- = 0 | 4 |
| TME normal mode, C(n) to C(n-1) = 2.0 |  | -2.6 |  | 2.6 | mV | Normal mode; C(n) to C(n-1) = 2.0 | 4 |
| TME normal mode, GPIO(n) to V- = 2.0, full temp range |  | -2.8 |  | 2.8 | mV | Normal mode; C(n) to C(n-1), GPIO(n) to V- = 2.0, apply over the full specified temperature range | 4 |
| TME normal mode, C(n) to C(n-1) = 3.3 |  | -3 |  | 3 | mV | Normal mode; C(n) to C(n-1) = 3.3 | 4 |
| TME normal mode, GPIO(n) to V- = 3.3, full temp range |  | -4 |  | 4 | mV | Normal mode; C(n) to C(n-1), GPIO(n) to V- = 3.3, apply over the full specified temperature range | 4 |
| TME normal mode, C(n) to C(n-1) = 4.2 |  | -3.8 |  | 3.8 | mV | Normal mode; C(n) to C(n-1) = 4.2 | 4 |
| TME normal mode, GPIO(n) to V- = 4.2, full temp range |  | -4.8 |  | 4.8 | mV | Normal mode; C(n) to C(n-1), GPIO(n) to V- = 4.2, apply over the full specified temperature range | 4 |
| TME normal mode, GPIO(n) to V- = 5.0 |  | -1 |  | 1 | mV | Normal mode; C(n) to C(n-1), GPIO(n) to V- = 5.0 | 4 |
| TME normal mode, sum of all cells |  | -0.35 |  | 0.35 | % | Normal mode; sum of all cells, apply over the full specified temperature range (printed +/-0.05 typ, +/-0.35 max) | 4 |
| TME normal mode, internal temperature |  | -5 |  | 5 | °C | Normal mode; internal temperature, T = maximum specified temperature | 4 |
| TME normal mode, VREG pin | VREG | -1 | -0.15 | 0 | % | Normal mode; VREG pin, apply over the full specified temperature range | 4 |
| TME normal mode, VREF2 pin | VREF2 | -0.05 | 0.05 | 0.2 | % | Normal mode; VREF2 pin, apply over the full specified temperature range | 4 |
| TME normal mode, digital supply VREGD | VREGD | -0.5 | 0.5 | 1.5 | % | Normal mode; digital supply voltage VREGD, apply over the full specified temperature range | 4 |
| TME filtered mode, C(n) to C(n-1), GPIO(n) to V- = 0 |  | -0.1 |  | 0.1 | mV | Filtered mode; C(n) to C(n-1), GPIO(n) to V- = 0 | 4 |
| TME filtered mode, C(n) to C(n-1) = 2.0 |  | -1.6 |  | 1.6 | mV | Filtered mode; C(n) to C(n-1) = 2.0 | 4 |
| TME filtered mode, GPIO(n) to V- = 2.0, full temp range |  | -1.8 |  | 1.8 | mV | Filtered mode; C(n) to C(n-1), GPIO(n) to V- = 2.0, apply over the full specified temperature range | 4 |
| TME filtered mode, C(n) to C(n-1) = 3.3 |  | -2.2 |  | 2.2 | mV | Filtered mode; C(n) to C(n-1) = 3.3 | 4 |
| TME filtered mode, GPIO(n) to V- = 3.3, full temp range |  | -3 |  | 3 | mV | Filtered mode; C(n) to C(n-1), GPIO(n) to V- = 3.3, apply over the full specified temperature range | 4 |
| TME filtered mode, C(n) to C(n-1) = 4.2 |  | -2.8 |  | 2.8 | mV | Filtered mode; C(n) to C(n-1) = 4.2 | 4 |
| TME filtered mode, GPIO(n) to V- = 4.2, full temp range |  | -3.8 |  | 3.8 | mV | Filtered mode; C(n) to C(n-1), GPIO(n) to V- = 4.2, apply over the full specified temperature range | 4 |
| TME filtered mode, GPIO(n) to V- = 5.0 |  | -1 |  | 1 | mV | Filtered mode; C(n) to C(n-1), GPIO(n) to V- = 5.0 | 4 |
| TME filtered mode, sum of all cells |  | -0.35 |  | 0.35 | % | Filtered mode; sum of all cells, apply over the full specified temperature range (printed +/-0.05 typ, +/-0.35 max) | 4 |
| TME filtered mode, internal temperature |  | -5 |  | 5 | °C | Filtered mode; internal temperature, T = maximum specified temperature | 4 |
| TME filtered mode, VREG pin | VREG | -1 | -0.15 | 0 | % | Filtered mode; VREG pin, apply over the full specified temperature range | 4 |
| TME filtered mode, VREF2 pin | VREF2 | -0.05 | 0.05 | 0.2 | % | Filtered mode; VREF2 pin, apply over the full specified temperature range | 4 |
| TME filtered mode, digital supply VREGD | VREGD | -0.5 | 0.8 | 1.5 | % | Filtered mode; digital supply voltage VREGD, apply over the full specified temperature range | 4 |
| 1st Reference Voltage | VREF1 | 3 | 3.15 | 3.3 | V | VREF1 pin, no load, apply over the full specified temperature range | 5 |
| 2nd Reference Voltage | VREF2 | 2.993 | 3 | 3.007 | V | VREF2 pin, no load, apply over the full specified temperature range | 5 |
| 2nd Reference Voltage with 5 kΩ load | VREF2 | 2.992 | 3 | 3.008 | V | VREF2 pin, 5 kΩ load to V-, apply over the full specified temperature range | 5 |
| V+ Supply Current, sleep | IVP | 3 |  | 5 | µA | State: core = sleep, isoSPI = idle, VREG = 5 V | 5 |
| V+ Supply Current, standby | IVP | 9 | 14 | 22 | µA | State: core = standby | 5 |
| V+ Supply Current, REFUP | IVP | 0.4 | 0.55 | 0.8 | mA | State: core = REFUP | 5 |
| V+ Supply Current, measure | IVP | 0.65 | 0.95 | 1.35 | mA | State: core = measure | 5 |
| VREG Supply Current, standby | IREG(CORE) | 10 | 35 | 60 | µA | State: core = standby | 6 |
| VREG Supply Current, REFUP | IREG(CORE) | 0.4 | 0.9 | 1.4 | mA | State: core = REFUP | 6 |
| VREG Supply Current, measure | IREG(CORE) | 14 | 15 | 16 | mA | State: core = measure | 6 |
| V+ Supply Voltage | V+ | 16 | 60 | 90 | V | TME specifications met, apply over the full specified temperature range | 6 |
| VREG Supply Voltage | VREG | 4.5 | 5 | 5.5 | V | TME supply rejection < 1 mV/V, apply over the full specified temperature range | 6 |
| DRIVE Output Voltage | DRIVE | 5.4 | 5.7 | 5.9 | V | Sourcing 1 µA | 6 |
| Digital Supply Voltage | VREGD | 2.7 | 3 | 3.6 | V | Apply over the full specified temperature range | 6 |
| Discharge Switch On Resistance |  | 4 |  | 10 | Ω | VCELL = 3.6 V, apply over the full specified temperature range | 6 |
| Data Return Delay | tRTN | 325 | 375 | 425 | ns | Apply over the full specified temperature range | 10 |
| Data Daisy-Chain Delay | tDSY(D) | 200 | 250 | 300 | ns | Apply over the full specified temperature range | 10 |
| Input Voltage (Relative to V-), C0 | C0 | -0.3 |  | 6 | V | Relative to V- | 11 |
| Input Voltage (Relative to V-), C18 | C18 | -0.3 |  |  | V | Relative to V-; max = MIN(V+ + 5.5 V, 112.5 V) | 11 |
| Input Voltage (Relative to V-), C(n), S(n) | C(n), S(n) | -0.3 |  |  | V | Relative to V-; max = MIN(8 × n, 112.5 V) | 11 |
| Input Voltage (Relative to V-), IPA, IMA, IPB, IMB | IPA, IMA, IPB, IMB | -0.3 |  |  | V | Relative to V-; max = VREG + 0.3 V, ≤ 6 V | 11 |
| Input Voltage (Relative to V-), DRIVE | DRIVE | -0.3 |  | 7 | V | Relative to V- | 11 |
| Input Voltage (Relative to V-), all other pins |  | -0.3 |  | 6 | V | Relative to V-; all other pins | 11 |
| Voltage Between Inputs, C(n) to C(n-1) and S(n) to C(n-1) |  | -0.3 |  | 8 | V | C(n) to C(n-1) and S(n) to C(n-1) | 11 |
| Voltage Between Inputs, C18 to C15 ... C3 to C0 |  | -0.3 |  | 21 | V | C18 to C15, C15 to C12, C12 to C9, C9 to C6, C6 to C3, C3 to C0 | 11 |
| Total Supply Voltage, V+ to V- | V+ to V- |  |  | 112.5 | V |  | 11 |
| Supply Voltage relative to C12, V+ to C12 | V+ to C12 |  |  | 50 | V | Relative to C12 | 11 |
| Current In and Out of Pins, all except VREG, IPA, IMA, IPB, IMB, C(n), S(n) |  |  |  | 10 | mA | All pins except VREG, IPA, IMA, IPB, IMB, C(n), and S(n) | 11 |
| Current In and Out of Pins, IPA, IMA, IPB, IMB | IPA, IMA, IPB, IMB |  |  | 30 | mA | IPA, IMA, IPB, and IMB | 11 |
| Specified Junction Temperature Range | TJ | -40 |  | 85 | °C | Specified junction temperature range | 11 |
| Junction Temperature (TJMAX) | TJMAX |  |  | 150 | °C |  | 11 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 11 |
| Thermal Resistance, junction to ambient (θJA) | θJA |  | 17 |  | °C/W | SW-64-2 (64-lead LQFP_EP); natural convection, one-cubic-foot sealed enclosure; board layout dependent | 11 |
| Thermal Resistance, junction to case (θJC) | θJC |  | 2.5 |  | °C/W | SW-64-2 (64-lead LQFP_EP) | 11 |

## CAD (KiCad official)

- Symbol: `ADBMS1818ASWZ-RL`
- Footprint: `Package_QFP:LQFP-64-1EP_10x10mm_P0.5mm_EP6.5x6.5mm`
- 3D model: LQFP-64-EP(10x10) (KiCad packages3D, STEP)
- 3D model files: `adbms1818aswz-rl-etched.step` / `adbms1818aswz-rl-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adbms1818aswz-rl.step` / `adbms1818aswz-rl.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589785203305574400) (89 pp, sha256 `fdab29ebeb2e5ec7`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/adbms1818aswz-rl-datasheet.pdf)