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ADBMS1818ASWAZ-R7

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Analog Devices Battery Management, LQFP-64-EP(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADBMS1818ASWAZ-R7

Analog Devices · Battery Management · LQFP-64-EP(10x10)

ADBMS1818ASWAZ-R7 from Analog Devices, in a LQFP-64-EP(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 V+ power_in Positive supply pin; total supply voltage V+ to V- is rated to 112.5 V absolute maximum.
2 C0 input Cell input C0; input voltage relative to V- is limited to -0.3 V to +6 V.
3 S1 passive Balance input/output S1, connected through an internal N-channel discharge MOSFET between S1 and C0; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 1.
4 C1 input Cell input C1; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 1.
5 S2 passive Balance input/output S2, connected through an internal N-channel discharge MOSFET between S2 and C1; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 2.
6 C2 input Cell input C2; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 2.
7 S3 passive Balance input/output S3, connected through an internal N-channel discharge MOSFET between S3 and C2; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 3.
8 C3 input Cell input C3; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 3.
9 S4 passive Balance input/output S4, connected through an internal N-channel discharge MOSFET between S4 and C3; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 4.
10 C4 input Cell input C4; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 4.
11 S5 passive Balance input/output S5, connected through an internal N-channel discharge MOSFET between S5 and C4; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 5.
12 C5 input Cell input C5; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 5.
13 S6 passive Balance input/output S6, connected through an internal N-channel discharge MOSFET between S6 and C5; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 6.
14 C6 input Cell input C6; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 6.
15 S7 passive Balance input/output S7, connected through an internal N-channel discharge MOSFET between S7 and C6; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 7.
16 C7 input Cell input C7; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 7.
17 S8 passive Balance input/output S8, connected through an internal N-channel discharge MOSFET between S8 and C7; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 8.
18 C8 input Cell input C8; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 8.
19 S9 passive Balance input/output S9, connected through an internal N-channel discharge MOSFET between S9 and C8; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 9.
20 C9 input Cell input C9; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 9.
21 S10 passive Balance input/output S10, connected through an internal N-channel discharge MOSFET between S10 and C9; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 10.
22 C10 input Cell input C10; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 10.
23 S11 passive Balance input/output S11, connected through an internal N-channel discharge MOSFET between S11 and C10; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 11.
24 C11 input Cell input C11; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 11.
25 S12 passive Balance input/output S12, connected through an internal N-channel discharge MOSFET between S12 and C11; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 12.
26 C12 input Cell input C12; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 12.
27 S13 passive Balance input/output S13, connected through an internal N-channel discharge MOSFET between S13 and C12; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 13.
28 C13 input Cell input C13; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 13.
29 S14 passive Balance input/output S14, connected through an internal N-channel discharge MOSFET between S14 and C13; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 14.
30 C14 input Cell input C14; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 14.
31 S15 passive Balance input/output S15, connected through an internal N-channel discharge MOSFET between S15 and C14; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 15.
32 C15 input Cell input C15; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 15.
33 S16 passive Balance input/output S16, connected through an internal N-channel discharge MOSFET between S16 and C15; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 16.
34 C16 input Cell input C16; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 16.
35 S17 passive Balance input/output S17, connected through an internal N-channel discharge MOSFET between S17 and C16; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 17.
36 C17 input Cell input C17; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 17.
37 S18 passive Balance input/output S18, connected through an internal N-channel discharge MOSFET between S18 and C17; input voltage relative to V- is limited to -0.3 V to MIN(8 x n, 112.5 V) with n = 18.
38 C18 input Cell input C18; input voltage relative to V- is limited to -0.3 V to MIN(V+ + 5.5 V, 112.5 V).
39 GPIO1 bidirectional General-purpose I/O usable as digital input, digital output, or analog input with a measurement range from V- to 5 V.
40 GPIO2 bidirectional General-purpose I/O usable as digital input, digital output, or analog input with a measurement range from V- to 5 V.
41 GPIO3 bidirectional General-purpose I/O usable as digital input, digital output, or analog input (range V- to 5 V), and can also serve as an I2C or SPI port.
42 GPIO4 bidirectional General-purpose I/O usable as digital input, digital output, or analog input (range V- to 5 V), and can also serve as an I2C or SPI port.
43 GPIO5 bidirectional General-purpose I/O usable as digital input, digital output, or analog input (range V- to 5 V), and can also serve as an I2C or SPI port.
44 GPIO6 bidirectional General-purpose I/O usable as digital input, digital output, or analog input with a measurement range from V- to 5 V.
45 GPIO7 bidirectional General-purpose I/O usable as digital input, digital output, or analog input with a measurement range from V- to 5 V.
46 GPIO8 bidirectional General-purpose I/O usable as digital input, digital output, or analog input with a measurement range from V- to 5 V.
47 GPIO9 bidirectional General-purpose I/O usable as digital input, digital output, or analog input with a measurement range from V- to 5 V.
48 VREG power_out 5 V regulator pin; bypass with an external 1 uF capacitor.
49 DRIVE output Drive pin for an external NPN transistor: connect its base to DRIVE, collector to V+, and emitter to VREG.
50 VREF2 power_out Buffered second reference voltage for driving multiple 10 kOhm thermistors; bypass with an external 1 uF capacitor.
51 VREF1 power_out ADC reference voltage; bypass with an external 1 uF capacitor and no DC loads are allowed.
52 DTEN input Discharge timer enable; connect to VREG to enable the discharge timer.
53 SDI input 4-wire SPI serial data input (digital input); in isoSPI mode (ISOMD tied to VREG) this pin is not used.
54 SDO output 4-wire SPI serial data output, an open-drain NMOS output that requires a 5 kOhm pull-up resistor.
55 ISOMD input Serial interface mode select: tie to VREG for 2-wire isoSPI mode or to V- for 4-wire SPI mode.
56 WDT output Watchdog timer output, an open-drain NMOS; it goes high impedance if no valid command is received within 2 seconds, and may be left disconnected or pulled to VREG through 1 MOhm.
57 IBIAS passive Isolated interface current bias; tie through a resistor divider to V- to set the output current, with the pin at 2 V when isoSPI is enabled and IPA/IMA or IPB/IMB drive set to 20 times IB.
58 ICMP passive Isolated interface comparator threshold set; tie to a resistor divider between IBIAS and V- so the receiver thresholds equal half the ICMP voltage.
59 V- power_in Negative supply pin; V- pins 59 and 60 must be shorted together externally to the IC.
60 V- power_in Negative supply pin; V- pins 59 and 60 must be shorted together externally to the IC.
61 IMA bidirectional Isolated 2-wire serial interface port A negative terminal; IMA and IPA form a differential input/output pair.
62 IPA bidirectional Isolated 2-wire serial interface port A positive terminal; IPA and IMA form a differential input/output pair.
63 IMB bidirectional Isolated 2-wire serial interface port B negative terminal; IMB and IPB form a differential input/output pair.
64 IPB bidirectional Isolated 2-wire serial interface port B positive terminal; IPB and IMB form a differential input/output pair.
65 EPAD power_in Exposed pad (V-) that must be soldered to the PCB and connected to the V- plane for thermal management.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-64-EP(10x10)
Category Power Management (PMIC)
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
TME in Normal Mode, C(n) to C(n-1) = 2.0 -2.6 2.6 mV C(n) to C(n-1) = 2.0 4
TME in Normal Mode, C(n) to C(n-1) = 3.3 -3 3 mV C(n) to C(n-1) = 3.3 4
TME in Normal Mode, C(n) to C(n-1) = 4.2 -3.8 3.8 mV C(n) to C(n-1) = 4.2 4
TME in Normal Mode, GPIO(n) to V- = 5.0 -1 1 mV C(n) to C(n-1), GPIO(n) to V- = 5.0 4
TME in Normal Mode, sum of all cells -0.35 0.05 0.35 % Sum of all cells, apply over the full specified temperature range 4
TME in Normal Mode, VREG pin -1 -0.15 0 % VREG pin, apply over the full specified temperature range 4
TME in Normal Mode, VREF2 pin -0.05 0.05 0.2 % VREF2 pin, apply over the full specified temperature range 4
TME in Normal Mode, digital supply VREGD VREGD -0.5 0.5 1.5 % Digital supply voltage, VREGD, apply over the full specified temperature range 4
TME in Filtered Mode, C(n) to C(n-1) = 2.0 -1.6 1.6 mV C(n) to C(n-1) = 2.0 4
TME in Filtered Mode, C(n) to C(n-1) = 4.2 -2.8 2.8 mV C(n) to C(n-1) = 4.2 4
TME in Fast Mode, C(n) to C(n-1), GPIO(n) to V- = 0 -2 2 mV C(n) to C(n-1), GPIO(n) to V- = 0 4
TME in Fast Mode, GPIO(n) to V- = 5.0 -10 10 mV C(n) to C(n-1), GPIO(n) to V- = 5.0 4
Input Range C0 C0 0 1 V Apply over the full specified temperature range 5
Input Range GPIO(n) GPIO(n) 0 5 V GPIO(n), n = 1 to 9, apply over the full specified temperature range 5
Input Leakage Current (IL) When Inputs Are Not Being Measured, C(n) IL -250 10 250 nA C(n), n = 0 to 18, apply over the full specified temperature range 5
Input Leakage Current (IL) When Inputs Are Not Being Measured, GPIO(n) IL -250 10 250 nA GPIO(n), n = 1 to 9, apply over the full specified temperature range 5
Input Current When Inputs Are Being Measured, C(n) -1 1 µA C(n), n = 0 to 18; State: Core = Measure 5
Input Current When Inputs Are Being Measured, GPIO(n) -1 1 µA GPIO(n), n = 1 to 9; State: Core = Measure 5
Input Current During Open Wire Detection 70 100 130 µA Apply over the full specified temperature range 5
1st Reference Voltage (VREF1) VREF1 3 3.15 3.3 V VREF1 pin, no load, apply over the full specified temperature range 5
2nd Reference Voltage (VREF2) VREF2 2.993 3 3.007 V VREF2 pin, no load, apply over the full specified temperature range 5
2nd Reference Voltage (VREF2) with 5 kΩ load VREF2 2.992 3 3.008 V VREF2 pin, 5 kΩ load to V−, apply over the full specified temperature range 5
V+ Supply Current (IVP), sleep IVP 6.1 11 µA State: core = sleep, isoSPI = idle, VREG = 0 V 5
V+ Supply Current (IVP), sleep, VREG = 5 V IVP 3 5 µA State: core = sleep, isoSPI = idle, VREG = 5 V 5
V+ Supply Current (IVP), standby IVP 9 14 22 µA State: core = standby 5
V+ Supply Current (IVP), standby, full temperature range IVP 6 14 28 µA State: core = standby, apply over the full specified temperature range 5
V+ Supply Current (IVP), measure IVP 0.65 0.95 1.35 mA State: core = measure 5
V+ Supply Current (IVP), measure, full temperature range IVP 0.6 0.95 1.4 mA State: core = measure, apply over the full specified temperature range 6
VREG Supply Current (IREG(CORE)), measure IREG(CORE) 14 15 16 mA State: core = measure 6
VREG Supply Current (IREG(CORE)), measure, full temperature range IREG(CORE) 13.5 15 16.5 mA State: core = measure, apply over the full specified temperature range 6
VREG Supply Current (IREG(CORE)), standby IREG(CORE) 10 35 60 µA State: core = standby 6
Additional VREG Supply Current (IREG(isoSPI)), ready IREG(isoSPI) 3.6 4.5 5.2 mA ISOMD = 0, RB1 + RB2 = 2 kΩ, ready, apply over the full specified temperature range 6
Additional VREG Supply Current (IREG(isoSPI)), active IREG(isoSPI) 5.6 6.8 8.1 mA ISOMD = 0, RB1 + RB2 = 2 kΩ, active, apply over the full specified temperature range 6
Data Return Delay (tRTN) tRTN 325 375 425 ns Apply over the full specified temperature range 10
V+ Supply Voltage 16 60 90 V TME specifications met, apply over the full specified temperature range 6
VREG Supply Voltage (VREG) VREG 4.5 5 5.5 V TME supply rejection < 1 mV/V, apply over the full specified temperature range 6
DRIVE Output Voltage, sourcing 1 µA 5.4 5.7 5.9 V Sourcing 1 µA 6
DRIVE Output Voltage, sourcing 1 µA, full temperature range 5.2 5.7 6.1 V Sourcing 1 µA, apply over the full specified temperature range 6
DRIVE Output Voltage, sourcing 500 µA, full temperature range 5.1 5.7 6.1 V Sourcing 500 µA, apply over the full specified temperature range 6
Digital Supply Voltage (VREGD) VREGD 2.7 3 3.6 V Apply over the full specified temperature range 6
Discharge Switch On Resistance 4 10 Ω VCELL = 3.6 V, apply over the full specified temperature range 6
Input Voltage C0 (relative to V-) C0 -0.3 6 V Relative to V- 11
Input Voltage C18 (relative to V-) C18 -0.3 V Relative to V-; max printed as MIN(V+ + 5.5 V, 112.5 V) 11
Input Voltage C(n), S(n) (relative to V-) C(n), S(n) -0.3 V Relative to V-; max printed as MIN(8 × n, 112.5 V) 11
Input Voltage IPA, IMA, IPB, IMB (relative to V-) -0.3 6 V Upper limit VREG + 0.3 V, ≤ 6 V 11
Input Voltage DRIVE (relative to V-) DRIVE -0.3 7 V Relative to V- 11
Input Voltage All Other Pins (relative to V-) -0.3 6 V Relative to V- 11
Voltage Between Inputs C(n) to C(n-1) and S(n) to C(n-1) -0.3 8 V C(n) to C(n-1) and S(n) to C(n-1) 11
Voltage Between Inputs C18 to C15, C15 to C12, C12 to C9, C9 to C6, C6 to C3, C3 to C0 -0.3 21 V C18 to C15, C15 to C12, C12 to C9, C9 to C6, C6 to C3, and C3 to C0 11
Total Supply Voltage, V+ to V- V+ to V- 112.5 V 11
Supply Voltage (Relative to C12), V+ to C12 V+ to C12 50 V 11
Current In and Out of Pins (all pins except VREG, IPA, IMA, IPB, IMB, C(n), S(n)) 10 mA Current in and out of pins 11
Current In and Out of Pins, IPA, IMA, IPB, IMB 30 mA Current in and out of pins 11
Specified Junction Temperature Range -40 85 °C Row names ADBMS1818ASWZ and ADBMSASWAZ 11
Junction Temperature (TJMAX) TJMAX 150 °C 11
Storage Temperature Range -65 150 °C 11
ESD Withstand, Human Body Model (HBM) HBM -1000 1000 V Human body model per ANSI/ESDA/JEDEC JS-001; class 1C 11
ESD Withstand, Charged Device Model (CDM) CDM -750 750 V CDM per ANSI/ESDA/JEDEC JS-002; class C2b 11
Thermal Resistance, junction to ambient (SW-64-2) θJA 17 °C/W 11
Thermal Resistance, junction to case (SW-64-2) θJC 2.5 °C/W 11

CAD (KiCad official)

  • Symbol: ADBMS1818ASWAZ-R7
  • Footprint: Package_QFP:LQFP-64-1EP_10x10mm_P0.5mm_EP6.5x6.5mm
  • 3D model: LQFP-64-EP(10x10) (KiCad packages3D, STEP)
  • 3D model files: adbms1818aswaz-r7-etched.step / adbms1818aswaz-r7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adbms1818aswaz-r7.step / adbms1818aswaz-r7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (92 pp, sha256 36b07646ed2930be, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF