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ADAU1966AWBSTZ

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Analog Devices Digital To Analog Converters (DACs), LQFP-80(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionadau1966awbstzfactory-2.0.0extractor-text

Verified ADAU1966AWBSTZ

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 80 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADAU1966AWBSTZ · LQFP-80(14x14) · 80 pins
  • ✓copper: 80 copper pads, none touching another net
  • ✓datasheet: all 80 pin names found in the 52-page datasheet
  • ✓distributor: lcsc C654428, digikey 505-ADAU1966AWBSTZ-ND, mouser 584-ADAU1966AWBSTZ
  • ✓family: LQFP-80_14x14mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-sc1rjx7i/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 80 pins = 80 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 80 pins agree
  • ✓visibility: public, source open
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docs Publish 0.1.0 · Ray 1d ago
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adau1966awbstz-etched.glb Publish 0.1.0 · Ray 1d ago
adau1966awbstz-etched.step adau1966awbstz: factory component page (tier=mfr) · Ray 1d ago
adau1966awbstz-hero.glb adau1966awbstz: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
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README.md Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier mfr, 80 pins · Ray 1d ago

ADAU1966AWBSTZ

Analog Devices · Digital To Analog Converters (DACs) · LQFP-80(14x14)

ADAU1966AWBSTZ from Analog Devices, in a LQFP-80(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DAC_BIAS3 input DAC Bias 3 pin, AC coupled with a 470 nF capacitor to AGND3.
2 DAC_BIAS4 input DAC Bias 4 pin, AC coupled with a 470 nF capacitor to AVDD3.
3 AVDD3 power_in Analog power supply pin for the AVDD3 group, which the datasheet specifies at 3.3 V.
4 DAC13P output DAC13 positive analog audio output.
5 DAC13N output DAC13 negative analog audio output.
6 DAC14P output DAC14 positive analog audio output.
7 DAC14N output DAC14 negative analog audio output.
8 DAC15P output DAC15 positive analog audio output.
9 DAC15N output DAC15 negative analog audio output.
10 DAC16P output DAC16 positive analog audio output.
11 DAC16N output DAC16 negative analog audio output.
12 AVDD4 power_in Analog power supply pin for the AVDD4 group, which the datasheet specifies at 3.3 V.
13 AGND4 power_in Analog ground pin.
14 PLLGND power_in PLL ground pin.
15 LF output PLL loop filter pin, referenced to PLLVDD.
16 PLLVDD power_in PLL power pin, to which 2.5 V must be applied to power the PLL.
17 MCLKI/XTALI input Master clock input or input to the crystal inverter; a multifunction pin.
18 XTALO output Output from the crystal inverter.
19 MCLKO output Master clock output, which can be a buffered MCLKI or a scaled clock selected by MCLKO_SEL.
20 DVDD power_in Digital power supply pin, 2.5 V.
21 DGND power_in Digital ground pin.
22 IOVDD power_in Power supply for digital input and output pins, 3.3 V.
23 VSENSE input 2.5 V regulator output and pass transistor collector, to be bypassed with 10 μF in parallel with 100 nF.
24 VDRIVE output Pass transistor base driver output for the internal 2.5 V regulator.
25 VSUPPLY input 3.3 V voltage regulator input and pass transistor emitter, to be bypassed with 10 μF in parallel with 100 nF.
26 DGND power_in Digital ground pin.
27 DBCLK bidirectional Bit clock for the DACs, which is an input in slave mode and an output in master mode.
28 DLRCLK bidirectional Frame clock for the DACs, which is an input in slave mode and an output in master mode.
29 DVDD power_in Digital power supply pin, 2.5 V.
30 DGND power_in Digital ground pin.
31 SA1 input Standalone mode TDM state input, tied to GND or IOVDD to select the TDM mode.
32 SA2 input Standalone mode TDM state input, tied to GND or IOVDD to select the TDM mode.
33 DSDATA6 input Serial data input for DAC11 and DAC12.
34 DSDATA5 input Serial data input for DAC9 and DAC10.
35 DSDATA4 input Serial data input for DAC7 and DAC8.
36 DSDATA3 input Serial data input for DAC5 and DAC6.
37 DSDATA2 input Serial data input for DAC3 and DAC4.
38 DSDATA1 input Serial data input for DAC1 and DAC2.
39 IOVDD power_in Power supply for digital input and output pins, 3.3 V.
40 DGND power_in Digital ground pin.
41 DVDD power_in Digital power supply pin, 2.5 V.
42 MOSI/ADDR1/SA input SPI master output slave input, I2C address 1, or SA_MODE state, a multifunction pin.
43 MISO/SDA/SA bidirectional SPI master input slave output, I2C control data (open-drain, requires a 2 kΩ pull-up), or SA_MODE state.
44 SCLK/SCL input SPI serial clock input or I2C control clock input.
45 SS/ADDR0/SA input SPI slave select (active low), I2C address 0, or SA_MODE state, a multifunction pin.
46 SA_MODE input Standalone mode select pin; tying it to IOVDD enables standalone mode.
47 PU/RST input Power-up/reset pin, active low, which disables all functionality until asserted high.
48 AGND1 power_in Analog ground pin.
49 AVDD1 power_in Analog power supply pin for the AVDD1 group, which the datasheet specifies at 3.3 V.
50 DAC1P output DAC1 positive analog audio output.
51 DAC1N output DAC1 negative analog audio output.
52 DAC2P output DAC2 positive analog audio output.
53 DAC2N output DAC2 negative analog audio output.
54 DAC3P output DAC3 positive analog audio output.
55 DAC3N output DAC3 negative analog audio output.
56 DAC4P output DAC4 positive analog audio output.
57 DAC4N output DAC4 negative analog audio output.
58 AVDD2 power_in Analog power supply pin for the AVDD2 group, which the datasheet specifies at 3.3 V.
59 DAC_BIAS1 input DAC bias 1 pin, AC coupled with a 470 nF capacitor to AVDD2.
60 DAC_BIAS2 input DAC bias 2 pin, AC coupled with a 470 nF capacitor to AGND2.
61 AGND2 power_in Analog ground pin.
62 CM output Common-mode reference filter capacitor connection, bypassed with 10 μF in parallel with 100 nF to AGND2 and optionally driven externally when VREF_EN is disabled.
63 TS_REF output Temperature sensor voltage reference filter capacitor connection, bypassed with 10 μF in parallel with 100 nF to AGND2.
64 DAC5P output DAC5 positive analog audio output.
65 DAC5N output DAC5 negative analog audio output.
66 DAC6P output DAC6 positive analog audio output.
67 DAC6N output DAC6 negative analog audio output.
68 DAC7P output DAC7 positive analog audio output.
69 DAC7N output DAC7 negative analog audio output.
70 DAC8P output DAC8 positive analog audio output.
71 DAC8N output DAC8 negative analog audio output.
72 DAC9P output DAC9 positive analog audio output.
73 DAC9N output DAC9 negative analog audio output.
74 DAC10P output DAC10 positive analog audio output.
75 DAC10N output DAC10 negative analog audio output.
76 DAC11P output DAC11 positive analog audio output.
77 DAC11N output DAC11 negative analog audio output.
78 DAC12P output DAC12 positive analog audio output.
79 DAC12N output DAC12 negative analog audio output.
80 AGND3 power_in Analog ground pin.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-80(14x14)
Category ADC/DAC/Data Conversion
Pins 80

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Dynamic Range No Filter differential DNR 105.5 111 dB 20 Hz to 20 kHz, -60 dB input; Differential output 3
Dynamic Range With A-Weighted Filter differential DNR 108.5 114 dB 20 Hz to 20 kHz, -60 dB input; Differential output 3
Dynamic Range No Filter single-ended DNR 102.5 107 dB 20 Hz to 20 kHz, -60 dB input; Single-ended output 3
Dynamic Range With A-Weighted Filter single-ended DNR 105.5 110 dB 20 Hz to 20 kHz, -60 dB input; Single-ended output 3
Total Harmonic Distortion + Noise differential output THD+N -97 -85 dB Two channels running -1 dBFS; All channels running -1 dBFS 3
Total Harmonic Distortion + Noise single-ended output THD+N -95 -80 dB Two channels running -1 dBFS; All channels running -1 dBFS 3
Gain Error -10 10 % 3
Offset Error -25 -6 25 mV 3
Gain Drift -30 30 ppm/°C 3
De-Emphasis Gain Error -0.6 0.6 dB 3
Temperature Accuracy -3 3 °C 3
Temperature Readout Range -60 140 °C 3
Common-Mode Reference Output CM 1.4 1.5 1.56 V CM pin 3
External Reference Voltage Source CM 1.4 1.5 1.56 V CM pin 3
Input Supply Voltage VSUPPLY 3.14 3.3 3.46 V VSUPPLY pin 3
Regulated Output Voltage VSENSE 2.25 2.5 2.59 V VSENSE pin 3
Full-Scale Differential Output Voltage 2 V rms Differential output 3
Full-Scale Differential Output Voltage 2.83 V p-p Differential output 3
Full-Scale Single-Ended Output Voltage 1 V rms Single-ended output 3
Full-Scale Single-Ended Output Voltage 1.41 V p-p Single-ended output 3
Interchannel Isolation 100 dB 3
Volume Control Step 0.375 dB 3
Volume Control Range 95.25 dB 3
Output Resistance at Each Pin 33 Ω 3
Temperature Readout Step Size 1 °C 3
Temperature Sample Rate 0.25 6 Hz 3
SCLK frequency fSCLK 10 MHz SPI port; not shown in Figure 19 7
SCL clock frequency fSCL 400 kHz I2C 7
Analog supply voltage AVDDx AVDDx -0.3 3.6 V 8
Input/Output supply voltage IOVDD -0.3 3.6 V 8
Digital supply voltage DVDD -0.3 3.6 V 8
PLL supply voltage PLLVDD -0.3 3.6 V 8
Supply voltage VSUPPLY -0.3 3.6 V 8
Input Current (Except Supply Pins) -20 20 mA 8
Analog Input Voltage (Signal Pins) -0.3 V Upper limit AVDDx + 0.3 V 8
Digital Input Voltage (Signal Pins) -0.3 V Upper limit DVDD + 0.3 V 8
Operating Temperature Range (Case) -40 125 °C Case 8
Storage Temperature Range -65 150 °C 8
Thermal resistance junction-to-ambient θJA 42.3 °C/W 80-Lead LQFP, 4-layer board with solid ground plane 8
Thermal resistance junction-to-case θJC 10 °C/W 80-Lead LQFP, 4-layer board with solid ground plane 8

CAD (KiCad official)

  • Symbol: ADAU1966AWBSTZ
  • Footprint: Package_QFP:LQFP-80_14x14mm_P0.65mm
  • 3D model: LQFP-80(14x14) (KiCad packages3D, STEP)
  • 3D model files: adau1966awbstz-etched.step / adau1966awbstz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adau1966awbstz.step / adau1966awbstz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (52 pp, sha256 d4ffc73dd043b20f, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF