component
ADAU1701JSTZ
Public Made by Adomby adom
Analog Devices Audio Interface ICs, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+84@@ -0,0 +1,84 @@+# ADAU1701JSTZ++**Analog Devices** · Audio Interface ICs · LQFP-48(7x7)++ADAU1701JSTZ from Analog Devices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AGND | power_in | Analog Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to AVDD. |+| 2 | ADC0 | input | Analog Audio Input 0 with full-scale input current of 100 μA rms (2 V rms with 18 kΩ external resistor). |+| 3 | ADC_RES | input | ADC Reference Current input; set full-scale current with external 18 kΩ resistor connected between this pin and ground. |+| 4 | ADC1 | input | Analog Audio Input 1 with full-scale input current of 100 μA rms (2 V rms with 18 kΩ external resistor). |+| 5 | RESET | input | Active Low Reset Input; reset triggered on high-to-low edge, device exits reset on low-to-high edge with 20 ns minimum low pulse width. |+| 6 | SELFBOOT | input | Enable/Disable Self-Boot; high initiates self-boot operation when brought out of reset, low selects control port mode. |+| 7 | ADDR0 | input | I2C and SPI Address 0; used in combination with ADDR1 to set I2C address or to distinguish between two ICs on common SPI CLATCH line. |+| 8 | MP4 | bidirectional | Multipurpose GPIO or Serial Input Port LRCLK (INPUT_LRCLK) with configurable debounce. |+| 9 | MP5 | bidirectional | Multipurpose GPIO or Serial Input Port BCLK (INPUT_BCLK) with minimum 40 ns pulse widths. |+| 10 | MP1 | bidirectional | Multipurpose GPIO or Serial Input Port Data 1 (SDATA_IN0) with configurable function. |+| 11 | MP0 | bidirectional | Multipurpose GPIO or Serial Input Port Data 0 (SDATA_IN1) with configurable function. |+| 12 | DGND | power_in | Digital Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to DVDD. |+| 13 | DVDD | power_in | 1.8 V Digital Supply; can be generated from 3.3 V with on-board regulator or supplied externally with 100 nF decouple capacitor. |+| 14 | MP7 | bidirectional | Multipurpose GPIO or Serial Output Port Data 1 (SDATA_OUT1) with 2 mA drive capability. |+| 15 | MP6 | bidirectional | Multipurpose GPIO, Serial Output Port Data 0, or TDM Data Output (SDATA_OUT0) with 2 mA drive capability. |+| 16 | MP10 | bidirectional | Multipurpose GPIO or Serial Output Port LRCLK (OUTPUT_LRCLK) configurable as master or slave. |+| 17 | VDRIVE | output | 1.8 V Regulator Drive output; provides base drive signal for external PNP regulator transistor. |+| 18 | IOVDD | power_in | Supply for Input and Output Pins (3.3 V); sets highest input voltage for digital inputs and supply for control port and MP pin outputs. |+| 19 | MP11 | bidirectional | Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK) configurable as master or slave with 2 mA drive. |+| 20 | ADDR1/CDATA/WB | input | Multifunction I2C Address 1 / SPI Data Input / EEPROM Write Back Trigger pin; sets I2C address, carries SPI data, or triggers writeback on rising edge. |+| 21 | CLATCH/WP | bidirectional | Multifunction SPI Latch Signal / Self-Boot EEPROM Write Protect pin; acts as SPI latch input or open-collector EEPROM write protect output. |+| 22 | SDA/COUT | bidirectional | Multifunction I2C Data / SPI Data Output pin; open-collector I2C with 2.2 kΩ pull-up or tri-stated SPI output. |+| 23 | SCL/CCLK | bidirectional | Multifunction I2C Clock / SPI Clock pin; open-collector I2C input in control mode, open-collector master output in self-boot mode, or SPI clock input. |+| 24 | DVDD | power_in | 1.8 V Digital Supply; can be generated from 3.3 V with on-board regulator or supplied externally with 100 nF decouple capacitor. |+| 25 | DGND | power_in | Digital Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to DVDD. |+| 26 | MP9 | bidirectional | Multipurpose GPIO, Serial Output Port Data 3 (SDATA_OUT3), or Auxiliary ADC Input 0 with 2 mA drive. |+| 27 | MP8 | bidirectional | Multipurpose GPIO, Serial Output Port Data 2 (SDATA_OUT2), or Auxiliary ADC Input 3 with 2 mA drive. |+| 28 | MP3 | bidirectional | Multipurpose GPIO, Serial Input Port Data 3 (SDATA_IN3), or Auxiliary ADC Input 2 with configurable function. |+| 29 | MP2 | bidirectional | Multipurpose GPIO, Serial Input Port Data 2 (SDATA_IN2), or Auxiliary ADC Input 1 with configurable function. |+| 30 | RSVD | unconnected | Reserved pin; must be tied to ground either directly or through a pull-down resistor for proper operation. |+| 31 | OSCO | output | Crystal Oscillator Circuit Output with 100 Ω damping resistor connection; do not use directly to drive clock to other ICs. |+| 32 | MCLKI | input | Master Clock Input; connect to 3.3 V clock signal or crystal oscillator output (3 μA input leakage). |+| 33 | PGND | power_in | PLL Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to PVDD. |+| 34 | PVDD | power_in | 3.3 V Power Supply for PLL and Auxiliary ADC Analog Section with 100 nF decouple capacitor to PGND. |+| 35 | PLL_LF | output | PLL Loop Filter analog output; connect two capacitors (3.3 nF and 56 nF) and one 475 Ω resistor to this pin. |+| 36 | AVDD | power_in | 3.3V Analog Supply with 100 nF decouple capacitor to AGND. |+| 37 | AGND | power_in | Analog Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to AVDD. |+| 38 | PLL_MODE0 | input | PLL Mode Setting bit 0; sets master clock PLL output frequency (64×fS, 256×fS, 384×fS, or 512×fS). |+| 39 | PLL_MODE1 | input | PLL Mode Setting bit 1; sets master clock PLL output frequency (64×fS, 256×fS, 384×fS, or 512×fS). |+| 40 | CM | output | 1.5 V Common-Mode Reference analog output; connect 47 μF decoupling capacitor to ground to reduce ADC-DAC crosstalk. |+| 41 | FILTD | output | DAC Filter Decoupling analog output (1.5 V); connect 10 μF capacitor between this pin and ground. |+| 42 | AGND | power_in | Analog Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to AVDD. |+| 43 | VOUT3 | output | DAC3 analog output with full-scale output voltage of 0.9 V rms; use with active or passive reconstruction filter. |+| 44 | VOUT2 | output | DAC2 analog output with full-scale output voltage of 0.9 V rms; use with active or passive reconstruction filter. |+| 45 | VOUT1 | output | DAC1 analog output with full-scale output voltage of 0.9 V rms; use with active or passive reconstruction filter. |+| 46 | VOUT0 | output | DAC0 analog output with full-scale output voltage of 0.9 V rms; use with active or passive reconstruction filter. |+| 47 | FILTA | output | ADC Filter Decoupling analog output (1.5 V); connect 10 μF capacitor between this pin and ground. |+| 48 | AVDD | power_in | 3.3V Analog Supply with 100 nF decouple capacitor to AGND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | LQFP-48(7x7) |+| Category | Interface |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `ADAU1701JSTZ`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `adau1701jstz-etched.step` / `adau1701jstz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adau1701jstz.step` / `adau1701jstz.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590230602801704960) (52 pp, sha256 `417167d2fd3dd077`, retrieved 2026-09-22, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adau1701jstz-datasheet.pdf)
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Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "adau1701jstz",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "adau1701jstz.kicad_sym",+ "adau1701jstz.kicad_mod",+ "adau1701jstz.glb",+ "adau1701jstz.step",+ "adau1701jstz.lbr",+ "docs/hero.png",+ "docs/adau1701jstz-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "ADAU1701JSTZ",+ "manufacturer": "Analog Devices",+ "package": "LQFP-48(7x7)",+ "pin_count": 48,+ "category": "Interface",+ "subcategory": "Audio Interface ICs",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590230602801704960",+ "parts": {+ "symbol": "adau1701jstz.kicad_sym",+ "footprint": "adau1701jstz.kicad_mod",+ "model_3d": "adau1701jstz-etched.glb",+ "model_3d_plain": "adau1701jstz.glb",+ "model_3d_step": "adau1701jstz-etched.step",+ "model_3d_step_plain": "adau1701jstz.step",+ "lbr": "adau1701jstz.lbr"+ },+ "distributor_links": {+ "lcsc": "C3001875"+ },+ "pins": [+ {+ "number": "1",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to AVDD."+ },+ {+ "number": "2",+ "name": "ADC0",+ "type": "input",+ "description": "Analog Audio Input 0 with full-scale input current of 100 μA rms (2 V rms with 18 kΩ external resistor)."+ },+ {+ "number": "3",+ "name": "ADC_RES",+ "type": "input",+ "description": "ADC Reference Current input; set full-scale current with external 18 kΩ resistor connected between this pin and ground."+ },+ {+ "number": "4",+ "name": "ADC1",+ "type": "input",+ "description": "Analog Audio Input 1 with full-scale input current of 100 μA rms (2 V rms with 18 kΩ external resistor)."+ },+ {+ "number": "5",+ "name": "RESET",+ "type": "input",+ "description": "Active Low Reset Input; reset triggered on high-to-low edge, device exits reset on low-to-high edge with 20 ns minimum low pulse width."+ },+ {+ "number": "6",+ "name": "SELFBOOT",+ "type": "input",+ "description": "Enable/Disable Self-Boot; high initiates self-boot operation when brought out of reset, low selects control port mode."+ },+ {+ "number": "7",+ "name": "ADDR0",+ "type": "input",+ "description": "I2C and SPI Address 0; used in combination with ADDR1 to set I2C address or to distinguish between two ICs on common SPI CLATCH line."+ },+ {+ "number": "8",+ "name": "MP4",+ "type": "bidirectional",+ "description": "Multipurpose GPIO or Serial Input Port LRCLK (INPUT_LRCLK) with configurable debounce."+ },+ {+ "number": "9",+ "name": "MP5",+ "type": "bidirectional",+ "description": "Multipurpose GPIO or Serial Input Port BCLK (INPUT_BCLK) with minimum 40 ns pulse widths."+ },+ {+ "number": "10",+ "name": "MP1",+ "type": "bidirectional",+ "description": "Multipurpose GPIO or Serial Input Port Data 1 (SDATA_IN0) with configurable function."+ },+ {+ "number": "11",+ "name": "MP0",+ "type": "bidirectional",+ "description": "Multipurpose GPIO or Serial Input Port Data 0 (SDATA_IN1) with configurable function."+ },+ {+ "number": "12",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to DVDD."+ },+ {+ "number": "13",+ "name": "DVDD",+ "type": "power_in",+ "description": "1.8 V Digital Supply; can be generated from 3.3 V with on-board regulator or supplied externally with 100 nF decouple capacitor."+ },+ {+ "number": "14",+ "name": "MP7",+ "type": "bidirectional",+ "description": "Multipurpose GPIO or Serial Output Port Data 1 (SDATA_OUT1) with 2 mA drive capability."+ },+ {+ "number": "15",+ "name": "MP6",+ "type": "bidirectional",+ "description": "Multipurpose GPIO, Serial Output Port Data 0, or TDM Data Output (SDATA_OUT0) with 2 mA drive capability."+ },+ {+ "number": "16",+ "name": "MP10",+ "type": "bidirectional",+ "description": "Multipurpose GPIO or Serial Output Port LRCLK (OUTPUT_LRCLK) configurable as master or slave."+ },+ {+ "number": "17",+ "name": "VDRIVE",+ "type": "output",+ "description": "1.8 V Regulator Drive output; provides base drive signal for external PNP regulator transistor."+ },+ {+ "number": "18",+ "name": "IOVDD",+ "type": "power_in",+ "description": "Supply for Input and Output Pins (3.3 V); sets highest input voltage for digital inputs and supply for control port and MP pin outputs."+ },+ {+ "number": "19",+ "name": "MP11",+ "type": "bidirectional",+ "description": "Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK) configurable as master or slave with 2 mA drive."+ },+ {+ "number": "20",+ "name": "ADDR1/CDATA/WB",+ "type": "input",+ "description": "Multifunction I2C Address 1 / SPI Data Input / EEPROM Write Back Trigger pin; sets I2C address, carries SPI data, or triggers writeback on rising edge."+ },+ {+ "number": "21",+ "name": "CLATCH/WP",+ "type": "bidirectional",+ "description": "Multifunction SPI Latch Signal / Self-Boot EEPROM Write Protect pin; acts as SPI latch input or open-collector EEPROM write protect output."+ },+ {+ "number": "22",+ "name": "SDA/COUT",+ "type": "bidirectional",+ "description": "Multifunction I2C Data / SPI Data Output pin; open-collector I2C with 2.2 kΩ pull-up or tri-stated SPI output."+ },+ {+ "number": "23",+ "name": "SCL/CCLK",+ "type": "bidirectional",+ "description": "Multifunction I2C Clock / SPI Clock pin; open-collector I2C input in control mode, open-collector master output in self-boot mode, or SPI clock input."+ },+ {+ "number": "24",+ "name": "DVDD",+ "type": "power_in",+ "description": "1.8 V Digital Supply; can be generated from 3.3 V with on-board regulator or supplied externally with 100 nF decouple capacitor."+ },+ {+ "number": "25",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to DVDD."+ },+ {+ "number": "26",+ "name": "MP9",+ "type": "bidirectional",+ "description": "Multipurpose GPIO, Serial Output Port Data 3 (SDATA_OUT3), or Auxiliary ADC Input 0 with 2 mA drive."+ },+ {+ "number": "27",+ "name": "MP8",+ "type": "bidirectional",+ "description": "Multipurpose GPIO, Serial Output Port Data 2 (SDATA_OUT2), or Auxiliary ADC Input 3 with 2 mA drive."+ },+ {+ "number": "28",+ "name": "MP3",+ "type": "bidirectional",+ "description": "Multipurpose GPIO, Serial Input Port Data 3 (SDATA_IN3), or Auxiliary ADC Input 2 with configurable function."+ },+ {+ "number": "29",+ "name": "MP2",+ "type": "bidirectional",+ "description": "Multipurpose GPIO, Serial Input Port Data 2 (SDATA_IN2), or Auxiliary ADC Input 1 with configurable function."+ },+ {+ "number": "30",+ "name": "RSVD",+ "type": "unconnected",+ "description": "Reserved pin; must be tied to ground either directly or through a pull-down resistor for proper operation."+ },+ {+ "number": "31",+ "name": "OSCO",+ "type": "output",+ "description": "Crystal Oscillator Circuit Output with 100 Ω damping resistor connection; do not use directly to drive clock to other ICs."+ },+ {+ "number": "32",+ "name": "MCLKI",+ "type": "input",+ "description": "Master Clock Input; connect to 3.3 V clock signal or crystal oscillator output (3 μA input leakage)."+ },+ {+ "number": "33",+ "name": "PGND",+ "type": "power_in",+ "description": "PLL Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to PVDD."+ },+ {+ "number": "34",+ "name": "PVDD",+ "type": "power_in",+ "description": "3.3 V Power Supply for PLL and Auxiliary ADC Analog Section with 100 nF decouple capacitor to PGND."+ },+ {+ "number": "35",+ "name": "PLL_LF",+ "type": "output",+ "description": "PLL Loop Filter analog output; connect two capacitors (3.3 nF and 56 nF) and one 475 Ω resistor to this pin."+ },+ {+ "number": "36",+ "name": "AVDD",+ "type": "power_in",+ "description": "3.3V Analog Supply with 100 nF decouple capacitor to AGND."+ },+ {+ "number": "37",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to AVDD."+ },+ {+ "number": "38",+ "name": "PLL_MODE0",+ "type": "input",+ "description": "PLL Mode Setting bit 0; sets master clock PLL output frequency (64×fS, 256×fS, 384×fS, or 512×fS)."+ },+ {+ "number": "39",+ "name": "PLL_MODE1",+ "type": "input",+ "description": "PLL Mode Setting bit 1; sets master clock PLL output frequency (64×fS, 256×fS, 384×fS, or 512×fS)."+ },+ {+ "number": "40",+ "name": "CM",+ "type": "output",+ "description": "1.5 V Common-Mode Reference analog output; connect 47 μF decoupling capacitor to ground to reduce ADC-DAC crosstalk."+ },+ {+ "number": "41",+ "name": "FILTD",+ "type": "output",+ "description": "DAC Filter Decoupling analog output (1.5 V); connect 10 μF capacitor between this pin and ground."+ },+ {+ "number": "42",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to AVDD."+ },+ {+ "number": "43",+ "name": "VOUT3",+ "type": "output",+ "description": "DAC3 analog output with full-scale output voltage of 0.9 V rms; use with active or passive reconstruction filter."+ },+ {+ "number": "44",+ "name": "VOUT2",+ "type": "output",+ "description": "DAC2 analog output with full-scale output voltage of 0.9 V rms; use with active or passive reconstruction filter."+ },+ {+ "number": "45",+ "name": "VOUT1",+ "type": "output",+ "description": "DAC1 analog output with full-scale output voltage of 0.9 V rms; use with active or passive reconstruction filter."+ },+ {+ "number": "46",+ "name": "VOUT0",+ "type": "output",+ "description": "DAC0 analog output with full-scale output voltage of 0.9 V rms; use with active or passive reconstruction filter."+ },+ {+ "number": "47",+ "name": "FILTA",+ "type": "output",+ "description": "ADC Filter Decoupling analog output (1.5 V); connect 10 μF capacitor between this pin and ground."+ },+ {+ "number": "48",+ "name": "AVDD",+ "type": "power_in",+ "description": "3.3V Analog Supply with 100 nF decouple capacitor to AGND."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Multipurpose pins (MP0-MP11, pins 8-11, 14-16, 19, 26-29) are highly configurable and can function a; Control port pins (20-23, 7) operate in multiple modes depending on whether device is in I2C, SPI, o; Pin 30 (RSVD) is reserved and must be tied to ground; marked as unconnected type but requires extern"+ ],+ "pages_sent": 52,+ "cost_usd": 0.7331,+ "at": "2026-09-22T13:06:07"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590230602801704960",+ "pages": 52,+ "sha256": "417167d2fd3dd077",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}