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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADAU1701JSTZ

Analog Devices · Audio Interface ICs · LQFP-48(7x7)

ADAU1701JSTZ from Analog Devices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AGND	power_in	Analog Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to AVDD.
2	ADC0	input	Analog Audio Input 0 with full-scale input current of 100 μA rms (2 V rms with 18 kΩ external resistor).
3	ADC_RES	input	ADC Reference Current input; set full-scale current with external 18 kΩ resistor connected between this pin and ground.
4	ADC1	input	Analog Audio Input 1 with full-scale input current of 100 μA rms (2 V rms with 18 kΩ external resistor).
5	RESET	input	Active Low Reset Input; reset triggered on high-to-low edge, device exits reset on low-to-high edge with 20 ns minimum low pulse width.
6	SELFBOOT	input	Enable/Disable Self-Boot; high initiates self-boot operation when brought out of reset, low selects control port mode.
7	ADDR0	input	I2C and SPI Address 0; used in combination with ADDR1 to set I2C address or to distinguish between two ICs on common SPI CLATCH line.
8	MP4	bidirectional	Multipurpose GPIO or Serial Input Port LRCLK (INPUT_LRCLK) with configurable debounce.
9	MP5	bidirectional	Multipurpose GPIO or Serial Input Port BCLK (INPUT_BCLK) with minimum 40 ns pulse widths.
10	MP1	bidirectional	Multipurpose GPIO or Serial Input Port Data 1 (SDATA_IN0) with configurable function.
11	MP0	bidirectional	Multipurpose GPIO or Serial Input Port Data 0 (SDATA_IN1) with configurable function.
12	DGND	power_in	Digital Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to DVDD.
13	DVDD	power_in	1.8 V Digital Supply; can be generated from 3.3 V with on-board regulator or supplied externally with 100 nF decouple capacitor.
14	MP7	bidirectional	Multipurpose GPIO or Serial Output Port Data 1 (SDATA_OUT1) with 2 mA drive capability.
15	MP6	bidirectional	Multipurpose GPIO, Serial Output Port Data 0, or TDM Data Output (SDATA_OUT0) with 2 mA drive capability.
16	MP10	bidirectional	Multipurpose GPIO or Serial Output Port LRCLK (OUTPUT_LRCLK) configurable as master or slave.
17	VDRIVE	output	1.8 V Regulator Drive output; provides base drive signal for external PNP regulator transistor.
18	IOVDD	power_in	Supply for Input and Output Pins (3.3 V); sets highest input voltage for digital inputs and supply for control port and MP pin outputs.
19	MP11	bidirectional	Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK) configurable as master or slave with 2 mA drive.
20	ADDR1/CDATA/WB	input	Multifunction I2C Address 1 / SPI Data Input / EEPROM Write Back Trigger pin; sets I2C address, carries SPI data, or triggers writeback on rising edge.
21	CLATCH/WP	bidirectional	Multifunction SPI Latch Signal / Self-Boot EEPROM Write Protect pin; acts as SPI latch input or open-collector EEPROM write protect output.
22	SDA/COUT	bidirectional	Multifunction I2C Data / SPI Data Output pin; open-collector I2C with 2.2 kΩ pull-up or tri-stated SPI output.
23	SCL/CCLK	bidirectional	Multifunction I2C Clock / SPI Clock pin; open-collector I2C input in control mode, open-collector master output in self-boot mode, or SPI clock input.
24	DVDD	power_in	1.8 V Digital Supply; can be generated from 3.3 V with on-board regulator or supplied externally with 100 nF decouple capacitor.
25	DGND	power_in	Digital Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to DVDD.
26	MP9	bidirectional	Multipurpose GPIO, Serial Output Port Data 3 (SDATA_OUT3), or Auxiliary ADC Input 0 with 2 mA drive.
27	MP8	bidirectional	Multipurpose GPIO, Serial Output Port Data 2 (SDATA_OUT2), or Auxiliary ADC Input 3 with 2 mA drive.
28	MP3	bidirectional	Multipurpose GPIO, Serial Input Port Data 3 (SDATA_IN3), or Auxiliary ADC Input 2 with configurable function.
29	MP2	bidirectional	Multipurpose GPIO, Serial Input Port Data 2 (SDATA_IN2), or Auxiliary ADC Input 1 with configurable function.
30	RSVD	unconnected	Reserved pin; must be tied to ground either directly or through a pull-down resistor for proper operation.
31	OSCO	output	Crystal Oscillator Circuit Output with 100 Ω damping resistor connection; do not use directly to drive clock to other ICs.
32	MCLKI	input	Master Clock Input; connect to 3.3 V clock signal or crystal oscillator output (3 μA input leakage).
33	PGND	power_in	PLL Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to PVDD.
34	PVDD	power_in	3.3 V Power Supply for PLL and Auxiliary ADC Analog Section with 100 nF decouple capacitor to PGND.
35	PLL_LF	output	PLL Loop Filter analog output; connect two capacitors (3.3 nF and 56 nF) and one 475 Ω resistor to this pin.
36	AVDD	power_in	3.3V Analog Supply with 100 nF decouple capacitor to AGND.
37	AGND	power_in	Analog Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to AVDD.
38	PLL_MODE0	input	PLL Mode Setting bit 0; sets master clock PLL output frequency (64×fS, 256×fS, 384×fS, or 512×fS).
39	PLL_MODE1	input	PLL Mode Setting bit 1; sets master clock PLL output frequency (64×fS, 256×fS, 384×fS, or 512×fS).
40	CM	output	1.5 V Common-Mode Reference analog output; connect 47 μF decoupling capacitor to ground to reduce ADC-DAC crosstalk.
41	FILTD	output	DAC Filter Decoupling analog output (1.5 V); connect 10 μF capacitor between this pin and ground.
42	AGND	power_in	Analog Ground; tie AGND, DGND, and PGND together in a common ground plane with 100 nF decouple capacitor to AVDD.
43	VOUT3	output	DAC3 analog output with full-scale output voltage of 0.9 V rms; use with active or passive reconstruction filter.
44	VOUT2	output	DAC2 analog output with full-scale output voltage of 0.9 V rms; use with active or passive reconstruction filter.
45	VOUT1	output	DAC1 analog output with full-scale output voltage of 0.9 V rms; use with active or passive reconstruction filter.
46	VOUT0	output	DAC0 analog output with full-scale output voltage of 0.9 V rms; use with active or passive reconstruction filter.
47	FILTA	output	ADC Filter Decoupling analog output (1.5 V); connect 10 μF capacitor between this pin and ground.
48	AVDD	power_in	3.3V Analog Supply with 100 nF decouple capacitor to AGND.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LQFP-48(7x7)
Category	Interface
Pins	48

CAD (KiCad official)

Symbol: ADAU1701JSTZ
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: adau1701jstz-etched.step / adau1701jstz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adau1701jstz.step / adau1701jstz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (52 pp, sha256 417167d2fd3dd077, retrieved 2026-09-22, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF