ADAU1466WBCPZ300 from Analog Devices, in a LFCSP-72(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
2	IOVDD	power_in	Input/output supply, 1.8 V -5% to 3.3 V +10%; bypass to pin 1 (DGND) with decoupling capacitors.
3	VDRIVE	output	Base drive bias for the external PNP pass transistor of the digital supply regulator; connect to ground if DVDD is supplied externally.
4	SPDIFIN	input	Input to the integrated S/PDIF receiver; internally biased to IOVDD/2 and disconnected when not in use.
5	SPDIFOUT	output	Output of the integrated S/PDIF transmitter; internally biased to IOVDD/2 and disconnected when not in use.
6	AGND	power_in	Analog ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
7	AVDD	power_in	Analog (auxiliary ADC) supply; must be 3.3 V ±10% and bypassed to pin 6 (AGND).
8	AUXADC0	input	Auxiliary ADC input channel 0 with full scale at AVDD; disconnect when not in use.
9	AUXADC1	input	Auxiliary ADC input channel 1 with full scale at AVDD; disconnect when not in use.
10	AUXADC2	input	Auxiliary ADC input channel 2 with full scale at AVDD; disconnect when not in use.
11	AUXADC3	input	Auxiliary ADC input channel 3 with full scale at AVDD; disconnect when not in use.
12	AUXADC4	input	Auxiliary ADC input channel 4 with full scale at AVDD; disconnect when not in use.
13	AUXADC5	input	Auxiliary ADC input channel 5 with full scale at AVDD; disconnect when not in use.
14	PGND	power_in	PLL ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
15	PVDD	power_in	PLL supply; must be 3.3 V ±10% and bypassed to pin 14 (PGND).
16	PLLFILT	passive	PLL filter node; the internally generated voltage is typically between 1.65 V and 2.10 V.
17	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
18	IOVDD	power_in	Input/output supply, 1.8 V -5% to 3.3 V +10%; bypass to pin 17 (DGND) with decoupling capacitors.
19	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
20	DVDD	power_in	Digital supply; must be 1.2 V ±5%, supplied externally or by the internal regulator with external pass transistor, and bypassed to pin 19 (DGND).
21	XTALIN/MCLK	input	Crystal oscillator input or master clock input to the PLL; can be driven directly or by a crystal across pin 22 (XTALOUT).
22	XTALOUT	output	Crystal oscillator output for driving an external crystal; disconnect when not in use.
23	CLKOUT	output	Configurable master clock output at 1x, 2x, 4x, or 8x the frequency of the divided clock input to the PLL; disconnect when not in use.
24	RESET	input	Active-low reset input with pull-down; a reset is triggered on a high-to-low edge and exited on a low-to-high edge.
25	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
26	SS_M/MP0	bidirectional	SPI master slave select or multipurpose GPIO MP0; internal pull-up nominally 250 kΩ, and its state with SELFBOOT high and a RESET rising edge selects the self boot protocol.
27	MOSI_M/MP1	bidirectional	SPI master data output or multipurpose GPIO MP1; disconnect when not in use.
28	SCL_M/SCLK_M/MP2	bidirectional	I2C master serial clock (open collector, requires a 2.0 kΩ pull-up to IOVDD), SPI master clock, or multipurpose GPIO MP2.
29	SDA_M/MISO_M/MP3	bidirectional	I2C master serial data (open collector, requires a 2.0 kΩ pull-up to IOVDD), SPI master data input, or multipurpose GPIO MP3.
30	MISO/SDA	bidirectional	SPI slave data output or I2C slave serial data (open collector, requires a 2.0 kΩ pull-up to IOVDD); connect to IOVDD with 10.0 kΩ when unused.
31	SCLK/SCL	input	SPI slave serial clock or I2C slave serial clock; requires a 2.0 kΩ pull-up to IOVDD in I2C mode and 10.0 kΩ to IOVDD when unused.
32	MOSI/ADDR1	input	SPI slave data input or I2C slave address MSB (ADDR1) together with pin 33.
33	SS/ADDR0	input	SPI slave select or I2C slave address LSB (ADDR0) together with pin 32; nominal 250 kΩ pull-up.
34	SELFBOOT	input	Self boot select; logic high (IOVDD) initiates self boot on the next rising edge of RESET, and it may be tied to IOVDD or ground directly or through a 1.0 kΩ or larger resistor.
35	DVDD	power_in	Digital supply; must be 1.2 V ±5%, supplied externally or by the internal regulator, and bypassed to pin 36 (DGND).
36	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
37	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
38	IOVDD	power_in	Input/output supply, 1.8 V -5% to 3.3 V +10%; bypass to pin 37 (DGND) with decoupling capacitors.
39	LRCLK_OUT0/MP4	bidirectional	Frame clock of serial output port 0 (master or slave direction) or multipurpose GPIO MP4; disconnect when not in use.
40	BCLK_OUT0	bidirectional	Bit clock of serial output port 0, bidirectional depending on master or slave operation; disconnect when not in use.
41	SDATA_OUT0	output	Serial data output port 0 for channels 0 to 15, supporting 2, 4, 8, and 16-channel modes; disconnect when not in use.
42	LRCLK_OUT1/MP5	bidirectional	Frame clock of serial output port 1 (master or slave direction) or multipurpose GPIO MP5; disconnect when not in use.
43	BCLK_OUT1	bidirectional	Bit clock of serial output port 1, bidirectional depending on master or slave operation; disconnect when not in use.
44	SDATA_OUT1	output	Serial data output port 1 for channels 16 to 31, supporting 2, 4, 8, and 16-channel modes; disconnect when not in use.
45	MP6	bidirectional	Configurable multipurpose GPIO 6; disconnect when not in use.
46	MP7	bidirectional	Configurable multipurpose GPIO 7; disconnect when not in use.
47	LRCLK_OUT2/MP8	bidirectional	Frame clock of serial output port 2 (master or slave direction) or multipurpose GPIO MP8; disconnect when not in use.
48	BCLK_OUT2	bidirectional	Bit clock of serial output port 2, bidirectional depending on master or slave operation; disconnect when not in use.
49	SDATA_OUT2	output	Serial data output port 2 for channels 32 to 39, supporting 2, 4, 8-channel, or flexible TDM modes; disconnect when not in use.
50	LRCLK_OUT3/MP9	bidirectional	Frame clock of serial output port 3 (master or slave direction) or multipurpose GPIO MP9; disconnect when not in use.
51	BCLK_OUT3	bidirectional	Bit clock of serial output port 3, bidirectional depending on master or slave operation; disconnect when not in use.
52	SDATA_OUT3	output	Serial data output port 3 for channels 40 to 47, supporting 2, 4, 8-channel, and flexible TDM modes; disconnect when not in use.
53	DVDD	power_in	Digital supply; must be 1.2 V ±5%, supplied externally or by the internal regulator, and bypassed to pin 54 (DGND).
54	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
55	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
56	IOVDD	power_in	Input/output supply, 1.8 V -5% to 3.3 V +10%; bypass to pin 55 (DGND) with decoupling capacitors.
57	BCLK_IN0	bidirectional	Bit clock of serial input port 0, bidirectional depending on master or slave operation; disconnect when not in use.
58	LRCLK_IN0/MP10	bidirectional	Frame clock of serial input port 0 (master or slave direction) or multipurpose GPIO MP10; disconnect when not in use.
59	SDATA_IN0	input	Serial data input port 0 for channels 0 to 15, supporting 2, 4, 8, and 16-channel modes; disconnect when not in use.
60	BCLK_IN1	bidirectional	Bit clock of serial input port 1, bidirectional depending on master or slave operation; disconnect when not in use.
61	LRCLK_IN1/MP11	bidirectional	Frame clock of serial input port 1 (master or slave direction) or multipurpose GPIO MP11; disconnect when not in use.
62	SDATA_IN1	input	Serial data input port 1 for channels 16 to 31, supporting 2, 4, 8, and 16-channel modes; disconnect when not in use.
63	THD_M	passive	Thermal diode negative input; connect to the D- pin of an external temperature sensor IC and disconnect when not in use.
64	THD_P	passive	Thermal diode positive input; connect to the D+ pin of an external temperature sensor IC and disconnect when not in use.
65	BCLK_IN2	bidirectional	Bit clock of serial input port 2, bidirectional depending on master or slave operation; disconnect when not in use.
66	LRCLK_IN2/MP12	bidirectional	Frame clock of serial input port 2 (master or slave direction) or multipurpose GPIO MP12; disconnect when not in use.
67	SDATA_IN2	input	Serial data input port 2 for channels 32 to 39, supporting 2, 4, 8-channel, or flexible TDM modes; disconnect when not in use.
68	BCLK_IN3	bidirectional	Bit clock of serial input port 3, bidirectional depending on master or slave operation; disconnect when not in use.
69	LRCLK_IN3/MP13	bidirectional	Frame clock of serial input port 3 (master or slave direction) or multipurpose GPIO MP13; disconnect when not in use.
70	SDATA_IN3	input	Serial data input port 3 for channels 40 to 47, supporting 2, 4, 8-channel, or flexible TDM modes; disconnect when not in use.
71	DVDD	power_in	Digital supply; must be 1.2 V ±5%, supplied externally or by the internal regulator, and bypassed to pin 72 (DGND).
72	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
73	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-72(10x10)
Category	Embedded Processors & Controllers
Pins	73

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Analog Voltage (AVDD)	AVDD	2.97	3.3	3.63	V	Supply for analog circuitry, including auxiliary ADC	6
Digital Voltage (DVDD)	DVDD	1.14	1.2	1.26	V	Supply for digital circuitry, including the DSP core, ASRCs, and signal routing	6
PLL Voltage (PVDD)	PVDD	2.97	3.3	3.63	V	Supply for PLL circuitry	6
IOVDD Voltage	IOVDD	1.71	3.3	3.63	V	Supply for input/output circuitry, including pads and level shifters	6
Analog Current (AVDD)	IAVDD	1.36	1.66	2	mA		6
Analog Current Idle State	IAVDD	1	1.1	40	μA		6
Analog Current Reset State	IAVDD	1	1.1	40	μA		6
PLL Current (PVDD)	IPVDD	8.3	10.2	15	mA	12.288 MHz master clock; default PLL settings	6
PLL Current Idle State	IPVDD	18.4	18.7	40	μA	Power applied, PLL not configured	6
PLL Current Reset State	IPVDD	18.4	18.7	40	μA	Power applied, RESET held low	6
Digital Current (DVDD) Idle State	IDVDD	5.9	15.7	559	mA	Power applied, DSP not enabled	6
Digital Current (DVDD) Reset State	IDVDD	5.9	15.7	559	mA	Power applied, RESET held low	6
Crystal Oscillator Transconductance	gm	8.1	10.6	14.6	mS		6
Integrated Nonlinearity (INL)	INL	-2.5		2.5	LSB	Auxiliary ADC	8
Differential Nonlinearity (DNL)	DNL	-2.5		2.5	LSB	Auxiliary ADC	8
Gain Error		-2.5		2.5	LSB	Auxiliary ADC	8
Digital Input High Level (VIH)	VIH	1.71		3.3	V	IOVDD = 3.3 V	7
Digital Input Low Level (VIL)	VIL	0		1.71	V	IOVDD = 3.3 V	7
Digital Input High Level (VIH)	VIH	0.92		1.8	V	IOVDD = 1.8 V	7
Digital Input Low Level (VIL)	VIL	0		0.89	V	IOVDD = 1.8 V	7
Digital Output High Level (VOH)	VOH	3.09		3.3	V	IOVDD = 3.3 V; IOH = 1 mA	7
Digital Output Low Level (VOL)	VOL	0		0.26	V	IOVDD = 3.3 V; IOL = 1 mA	7
Digital Output High Level (VOH)	VOH	1.45		1.8	V	IOVDD = 1.8 V	7
Digital Output Low Level (VOL)	VOL	0		0.33	V	IOVDD = 1.8 V	7
SPI Slave SCLK Write Frequency	fSCLKWRITE			20	MHz	SCLK write frequency	14
SPI Slave SCLK Read Frequency	fSCLKREAD			20	MHz	SCLK read frequency	14
SPI Slave SCLK Pulse Width Low	tSCLKPWL	6			ns	SCLK = 20 MHz	14
SPI Slave SCLK Pulse Width High	tSCLKPWH	21			ns	SCLK = 20 MHz	14
SPI Slave SS Setup to SCLK Rising Edge	tSSS	1			ns		14
SPI Slave SS Hold from SCLK Rising Edge	tSSH	2			ns		14
SPI Slave SS Pulse Width High	tSSPWH	10			ns		14
SPI Slave MOSI Setup to SCLK Rising Edge	tMOSIS	1			ns		14
SPI Slave MOSI Hold from SCLK Rising Edge	tMOSIH	2			ns		14
SPI Slave MISO Valid Output Delay	tMISOD			39	ns	MISO valid output delay from SCLK falling edge	14
SPI Master Data Input Setup Time	tSSPIDM	15			ns	MISO_M data input valid to SCLK_M edge	15
SPI Master Data Input Hold Time	tHSPIDM	5			ns	SCLK_M last sampling edge to data input not valid	15
SPI Master Clock Cycle Period	tSPICLKM	41.7			ns	SPI master clock cycle period	15
SPI Master Clock Frequency	fSCLK_M			24	MHz	SPI master clock frequency	15
SPI Master SCLK_M High Period	tSPICHM	17			ns	fSCLK_M = 24 MHz	15
SPI Master SCLK_M Low Period	tSPICLM	17			ns	fSCLK_M = 24 MHz	15
SPI Master Data Out Delay	tDDSPIDM			16.9	ns	SCLK_M edge to data out valid, fSCLK_M = 24 MHz	15
SPI Master Data Out Hold Time	tHDSPIDM	21			ns	SCLK_M edge to data out not valid, fSCLK_M = 24 MHz	15
SPI Master SS_M Low to First SCLK_M Edge	tSDSCIM	36			ns	fSCLK_M = 24 MHz	15
SPI Master Last SCLK_M Edge to SS_M High	tHDSM	95			ns	fSCLK_M = 24 MHz	15
PDM Data Setup Time	tSETUP	10			ns	Data setup time	16
PDM Data Hold Time	tHOLD	5			ns	Data hold time	16
DVDD to Ground	DVDD	0		1.4	V		17
AVDD to Ground	AVDD	0		4	V		17
IOVDD to Ground	IOVDD	0		4	V		17
PVDD to Ground	PVDD	0		4	V		17
Maximum Ambient Temperature Range	TA	-40		105	°C		17
Maximum Junction Temperature	TJ			125	°C		17
Storage Temperature Range	TSTG	-65		150	°C		17
Soldering Temperature				300	°C	10 sec	17
Thermal Coefficient ψJT	ψJT		0.15		°C/W		17
Thermal Resistance Junction to Ambient	θJA		29.15		°C/W	JEDEC 2s2p thermal test PCB, 25 thermal vias, natural convection	17
Thermal Resistance Junction to Board	θJB		10.59		°C/W	JEDEC 2s2p thermal test PCB, 25 thermal vias	17
Thermal Resistance Junction to Case (Top)	θJCT		0.04		°C/W	Cold plate attached to exposed paddle	17
Thermal Resistance Junction to Case (Bottom)	θJCB		3.39		°C/W		17

CAD (KiCad official)

Symbol: ADAU1466WBCPZ300
Footprint: Package_DFN_QFN:QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
3D model: LFCSP-72(10x10) (KiCad packages3D, STEP)
3D model files: adau1466wbcpz300-etched.step / adau1466wbcpz300-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adau1466wbcpz300.step / adau1466wbcpz300.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (202 pp, sha256 c473f6316a5d3f95, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ADAU1466WBCPZ300

Verified ADAU1466WBCPZ300

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README