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Analog Devices Digital Signal Processors / Controllers (DSPs/DSCs), LFCSP-72(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADAU1462WBCPZ300

Analog Devices · Digital Signal Processors / Controllers (DSPs/DSCs) · LFCSP-72(10x10)

ADAU1462WBCPZ300 from Analog Devices, in a LFCSP-72(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane.
2	IOVDD	power_in	Input/output supply, 1.8 V − 5% to 3.3 V + 10%, bypassed with decoupling capacitors to Pin 1 (DGND).
3	VDRIVE	output	Base drive bias output for the external PNP pass transistor of the digital supply regulator; connect to ground if DVDD is supplied externally.
4	SPDIFIN	input	Input to the integrated S/PDIF receiver, internally biased to IOVDD/2; disconnect when not in use.
5	SPDIFOUT	output	Configurable output from the integrated S/PDIF transmitter, internally biased to IOVDD/2; disconnect when not in use.
6	AGND	power_in	Analog ground reference; tie all DGND, AGND and PGND pins together in a common ground plane.
7	AVDD	power_in	Analog (auxiliary ADC) supply, must be 3.3 V ± 10%, bypassed to Pin 6 (AGND).
8	AUXADC0	input	Auxiliary ADC input channel 0 read for use in the DSP program; disconnect when not in use.
9	AUXADC1	input	Auxiliary ADC input channel 1 read for use in the DSP program; disconnect when not in use.
10	AUXADC2	input	Auxiliary ADC input channel 2 read for use in the DSP program; disconnect when not in use.
11	AUXADC3	input	Auxiliary ADC input channel 3 read for use in the DSP program; disconnect when not in use.
12	AUXADC4	input	Auxiliary ADC input channel 4 read for use in the DSP program; disconnect when not in use.
13	AUXADC5	input	Auxiliary ADC input channel 5 read for use in the DSP program; disconnect when not in use.
14	PGND	power_in	PLL ground reference; tie all DGND, AGND and PGND pins together in a common ground plane.
15	PVDD	power_in	PLL supply, must be 3.3 V ± 10%, bypassed to Pin 14 (PGND).
16	PLLFILT	passive	PLL filter pin; the internally generated voltage is typically between 1.65 V and 2.10 V.
17	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane.
18	IOVDD	power_in	Input/output supply, 1.8 V − 5% to 3.3 V + 10%, bypassed to Pin 17 (DGND).
19	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane.
20	DVDD	power_in	Digital supply, must be 1.2 V ± 5%, supplied externally or via the internal regulator and external pass transistor; bypassed to Pin 19 (DGND).
21	XTALIN/MCLK	input	Crystal oscillator input or master clock input to the PLL, driven directly or by a crystal via XTALOUT.
22	XTALOUT	output	Crystal oscillator output for driving an external crystal; disconnect when not in use.
23	CLKOUT	output	Configurable master clock output at 1x, 2x, 4x or 8x the divided clock input to the PLL; disconnect when not in use.
24	RESET	input	Active-low reset input with internal pull-down; reset triggers on a high-to-low edge, exits on low-to-high, and sets all RAMs and registers to defaults.
25	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane.
26	SS_M/MP0	bidirectional	SPI master slave select or multipurpose GPIO 0 with nominal 250 kΩ pull-up; at self boot, floating selects SPI and a 10 kΩ pull-down to DGND selects I2C.
27	MOSI_M/MP1	bidirectional	SPI master data output or multipurpose GPIO 1 with disableable pull-up; disconnect when not in use.
28	SCL_M/SCLK_M/MP2	bidirectional	I2C master serial clock (open collector, 2.0 kΩ pull-up to IOVDD), SPI master clock, or multipurpose GPIO 2.
29	SDA_M/MISO_M/MP3	bidirectional	I2C master serial data (open collector, 2.0 kΩ pull-up to IOVDD), SPI master data input, or multipurpose GPIO 3.
30	MISO/SDA	bidirectional	SPI slave data output or I2C slave serial data (open collector, 2.0 kΩ pull-up to IOVDD); connect to IOVDD with 10.0 kΩ when unused.
31	SCLK/SCL	input	SPI slave serial clock or I2C slave serial clock input (2.0 kΩ pull-up to IOVDD for I2C); connect to IOVDD with 10.0 kΩ when unused.
32	MOSI/ADDR1	input	SPI slave data input or I2C slave address MSB (ADDR1) with disableable pull-up.
33	SS/ADDR0	input	SPI slave select or I2C slave address LSB (ADDR0) with nominal 250 kΩ pull-up.
34	SELFBOOT	input	Self boot select with pull-up; logic high (IOVDD) starts self boot from EEPROM on the next RESET rising edge, ground disables it.
35	DVDD	power_in	Digital supply, must be 1.2 V ± 5%, bypassed to Pin 36 (DGND).
36	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane.
37	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane.
38	IOVDD	power_in	Input/output supply, 1.8 V − 5% to 3.3 V + 10%, bypassed to Pin 37 (DGND).
39	LRCLK_OUT0/MP4	bidirectional	Frame clock for Serial Output Port 0 (direction set by master/slave mode) or multipurpose GPIO 4.
40	BCLK_OUT0	bidirectional	Bit clock for Serial Output Port 0, direction depending on master or slave mode.
41	SDATA_OUT0	output	Serial Output Port 0 data (Channel 0 to 15), supporting 2-, 4-, 8- and 16-channel modes.
42	LRCLK_OUT1/MP5	bidirectional	Frame clock for Serial Output Port 1 (direction set by master/slave mode) or multipurpose GPIO 5.
43	BCLK_OUT1	bidirectional	Bit clock for Serial Output Port 1, direction depending on master or slave mode.
44	SDATA_OUT1	output	Serial Output Port 1 data (Channel 16 to 31), supporting 2-, 4-, 8- and 16-channel modes.
45	MP6	bidirectional	Configurable multipurpose general-purpose input/output 6.
46	MP7	bidirectional	Configurable multipurpose general-purpose input/output 7.
47	LRCLK_OUT2/MP8	bidirectional	Frame clock for Serial Output Port 2 (direction set by master/slave mode) or multipurpose GPIO 8.
48	BCLK_OUT2	bidirectional	Bit clock for Serial Output Port 2, direction depending on master or slave mode.
49	SDATA_OUT2	output	Serial Output Port 2 data (Channel 32 to 39), supporting 2-, 4-, 8-channel or flexible TDM mode.
50	LRCLK_OUT3/MP9	bidirectional	Frame clock for Serial Output Port 3 (direction set by master/slave mode) or multipurpose GPIO 9.
51	BCLK_OUT3	bidirectional	Bit clock for Serial Output Port 3, direction depending on master or slave mode.
52	SDATA_OUT3	output	Serial Output Port 3 data (Channel 40 to 47), supporting 2-, 4-, 8-channel and flexible TDM modes.
53	DVDD	power_in	Digital supply, must be 1.2 V ± 5%, bypassed to Pin 54 (DGND).
54	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane.
55	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane.
56	IOVDD	power_in	Input/output supply, 1.8 V − 5% to 3.3 V + 10%, bypassed to Pin 55 (DGND).
57	BCLK_IN0	bidirectional	Bit clock for Serial Input Port 0, direction depending on master or slave mode.
58	LRCLK_IN0/MP10	bidirectional	Frame clock for Serial Input Port 0 (direction set by master/slave mode) or multipurpose GPIO 10.
59	SDATA_IN0	input	Serial Input Port 0 data (Channel 0 to 15), supporting 2-, 4-, 8- or 16-channel mode.
60	BCLK_IN1	bidirectional	Bit clock for Serial Input Port 1, direction depending on master or slave mode.
61	LRCLK_IN1/MP11	bidirectional	Frame clock for Serial Input Port 1 (direction set by master/slave mode) or multipurpose GPIO 11.
62	SDATA_IN1	input	Serial Input Port 1 data (Channel 16 to 31), supporting 2-, 4-, 8- or 16-channel mode.
63	THD_M	passive	Thermal diode negative input, connected to the D− pin of an external temperature sensor IC.
64	THD_P	passive	Thermal diode positive input, connected to the D+ pin of an external temperature sensor IC.
65	BCLK_IN2	bidirectional	Bit clock for Serial Input Port 2, direction depending on master or slave mode.
66	LRCLK_IN2/MP12	bidirectional	Frame clock for Serial Input Port 2 (direction set by master/slave mode) or multipurpose GPIO 12.
67	SDATA_IN2	input	Serial Input Port 2 data (Channel 32 to 39), supporting 2-, 4-, 8-channel or flexible TDM mode.
68	BCLK_IN3	bidirectional	Bit clock for Serial Input Port 3, direction depending on master or slave mode.
69	LRCLK_IN3/MP13	bidirectional	Frame clock for Serial Input Port 3 (direction set by master/slave mode) or multipurpose GPIO 13.
70	SDATA_IN3	input	Serial Input Port 3 data (Channel 40 to 47), supporting 2-, 4-, 8-channel or flexible TDM mode.
71	DVDD	power_in	Digital supply, must be 1.2 V ± 5%, bypassed to Pin 72 (DGND).
72	DGND	power_in	Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane.
73	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-72(10x10)
Category	Single Chip Microcomputer/Microcontroller
Pins	73

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Analog Voltage	AVDD	2.97	3.3	3.63	V	Supply for analog circuitry, including auxiliary ADC	6
Digital Voltage	DVDD	1.14	1.2	1.26	V	Supply for digital circuitry, including the DSP core, ASRCs, and signal routing	6
PLL Voltage	PVDD	2.97	3.3	3.63	V	Supply for PLL circuitry	6
IOVDD Voltage	IOVDD	1.71	3.3	3.63	V	Supply for input/output circuitry, including pads and level shifters	6
Analog Current (AVDD)		1.36	1.66	2	mA		6
Analog Current Idle State		1	1.1	40	μA		6
Analog Current Reset State		1	1.1	40	μA		6
PLL Current (PVDD)		8.3	10.2	15	mA	12.288 MHz master clock; default PLL settings	6
PLL Current Idle State		18.4	18.7	40	μA	Power applied, PLL not configured	6
PLL Current Reset State		18.4	18.7	40	μA	Power applied, RESET held low	6
I/O Current Power-Down State		4.1		4.3	mA	IOVDD = 1.8 V − 5% to 3.3 V + 10%	6
Digital Current Maximum Program, fCORE = 294.912 MHz			485	920	mA	ADAU1462 Operation State, fCORE = 294.912 MHz	6
Digital Current Typical Program, fCORE = 294.912 MHz			330		mA	Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active	6
Digital Current Minimal Program, fCORE = 294.912 MHz			213		mA	Test program includes 2-channel I/O, 10-band EQ per channel	6
Digital Current Idle State		5.9	15.7	559	mA	Power applied, DSP not enabled	6
Digital Current Reset State		5.9	15.7	559	mA	Power applied, RESET held low	6
ASRC I/O Sample Rate		6		192	kHz		6
ASRC Dynamic Range			139		dB	A-weighted, 20 Hz to 20 kHz	6
ASRC THD + N			-120		dB		6
Crystal Oscillator Transconductance		8.1	10.6	14.6	mS		6
Regulator DVDD Voltage		1.14	1.2		V	Regulator maintains typical output voltage up to a maximum 800 mA load; IOVDD = 1.8 V − 5% to 3.3 V + 10%	6
Input High Level	VIH	1.71		3.3	V	IOVDD = 3.3 V	7
Input Low Level	VIL	0		1.71	V	IOVDD = 3.3 V	7
Input High Level	VIH	0.92		1.8	V	IOVDD = 1.8 V	7
Input Low Level	VIL	0		0.89	V	IOVDD = 1.8 V	7
Output High Level	VOH	3.09		3.3	V	IOVDD = 3.3 V, IOH = 1 mA	7
Output Low Level	VOL	0		0.26	V	IOVDD = 3.3 V, IOL = 1 mA	7
Output High Level	VOH	1.45		1.8	V	IOVDD = 1.8 V	7
Output Low Level	VOL	0		0.33	V	IOVDD = 1.8 V	7
Input Capacitance	CI			2	pF	Guaranteed by design	7
Auxiliary ADC Resolution			10		Bits		8
Auxiliary ADC Integrated Nonlinearity	INL	-2.5		2.5	LSB		8
Auxiliary ADC Differential Nonlinearity	DNL	-2.5		2.5	LSB		8
Auxiliary ADC Gain Error		-2.5		2.5	LSB		8
Auxiliary ADC Input Impedance			200		kΩ		8
SCLK write frequency	fSCLKWRITE			20	MHz	SPI slave	14
SCLK read frequency	fSCLKREAD			20	MHz	SPI slave	14
SCLK pulse width low	tSCLKPWL	6			ns	SCLK = 20 MHz	14
SCLK pulse width high	tSCLKPWH	21			ns	SCLK = 20 MHz	14
MISO valid output delay	tMISOD			39	ns	from SCLK falling edge	14
SPI master clock frequency	fSCLK_M			24	MHz		15
PDM data setup time	tSETUP	10			ns		16
PDM data hold time	tHOLD	5			ns		16
DVDD to Ground		0		1.4	V		17
AVDD to Ground		0		4	V		17
IOVDD to Ground		0		4	V		17
PVDD to Ground		0		4	V		17
Maximum Ambient Temperature Range		-40		105	°C		17
Maximum Junction Temperature				125	°C		17
Storage Temperature Range		-65		150	°C		17
Soldering				300	°C	10 sec	17
Thermal coefficient ψJT	ψJT		0.15		°C/W	JEDEC 2s2p PCB, 25 thermal vias, natural convection	17
Thermal coefficient θJA	θJA		29.15		°C/W	JEDEC 2s2p PCB, 25 thermal vias, natural convection	17
Thermal coefficient θJB	θJB		10.59		°C/W	JEDEC 2s2p PCB, junction to board	17
Thermal coefficient θJCT	θJCT		0.04		°C/W	cold plate attached directly to exposed paddle	17
Thermal coefficient θJCB	θJCB		3.39		°C/W		17

CAD (KiCad official)

Symbol: ADAU1462WBCPZ300
Footprint: Package_DFN_QFN:QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
3D model: LFCSP-72(10x10), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: adau1462wbcpz300-etched.step / adau1462wbcpz300-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adau1462wbcpz300.step / adau1462wbcpz300.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (202 pp, sha256 c473f6316a5d3f95, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# ADAU1462WBCPZ300

**Analog Devices** · Digital Signal Processors / Controllers (DSPs/DSCs) · LFCSP-72(10x10)

ADAU1462WBCPZ300 from Analog Devices, in a LFCSP-72(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DGND | power_in | Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane. |
| 2 | IOVDD | power_in | Input/output supply, 1.8 V − 5% to 3.3 V + 10%, bypassed with decoupling capacitors to Pin 1 (DGND). |
| 3 | VDRIVE | output | Base drive bias output for the external PNP pass transistor of the digital supply regulator; connect to ground if DVDD is supplied externally. |
| 4 | SPDIFIN | input | Input to the integrated S/PDIF receiver, internally biased to IOVDD/2; disconnect when not in use. |
| 5 | SPDIFOUT | output | Configurable output from the integrated S/PDIF transmitter, internally biased to IOVDD/2; disconnect when not in use. |
| 6 | AGND | power_in | Analog ground reference; tie all DGND, AGND and PGND pins together in a common ground plane. |
| 7 | AVDD | power_in | Analog (auxiliary ADC) supply, must be 3.3 V ± 10%, bypassed to Pin 6 (AGND). |
| 8 | AUXADC0 | input | Auxiliary ADC input channel 0 read for use in the DSP program; disconnect when not in use. |
| 9 | AUXADC1 | input | Auxiliary ADC input channel 1 read for use in the DSP program; disconnect when not in use. |
| 10 | AUXADC2 | input | Auxiliary ADC input channel 2 read for use in the DSP program; disconnect when not in use. |
| 11 | AUXADC3 | input | Auxiliary ADC input channel 3 read for use in the DSP program; disconnect when not in use. |
| 12 | AUXADC4 | input | Auxiliary ADC input channel 4 read for use in the DSP program; disconnect when not in use. |
| 13 | AUXADC5 | input | Auxiliary ADC input channel 5 read for use in the DSP program; disconnect when not in use. |
| 14 | PGND | power_in | PLL ground reference; tie all DGND, AGND and PGND pins together in a common ground plane. |
| 15 | PVDD | power_in | PLL supply, must be 3.3 V ± 10%, bypassed to Pin 14 (PGND). |
| 16 | PLLFILT | passive | PLL filter pin; the internally generated voltage is typically between 1.65 V and 2.10 V. |
| 17 | DGND | power_in | Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane. |
| 18 | IOVDD | power_in | Input/output supply, 1.8 V − 5% to 3.3 V + 10%, bypassed to Pin 17 (DGND). |
| 19 | DGND | power_in | Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane. |
| 20 | DVDD | power_in | Digital supply, must be 1.2 V ± 5%, supplied externally or via the internal regulator and external pass transistor; bypassed to Pin 19 (DGND). |
| 21 | XTALIN/MCLK | input | Crystal oscillator input or master clock input to the PLL, driven directly or by a crystal via XTALOUT. |
| 22 | XTALOUT | output | Crystal oscillator output for driving an external crystal; disconnect when not in use. |
| 23 | CLKOUT | output | Configurable master clock output at 1x, 2x, 4x or 8x the divided clock input to the PLL; disconnect when not in use. |
| 24 | RESET | input | Active-low reset input with internal pull-down; reset triggers on a high-to-low edge, exits on low-to-high, and sets all RAMs and registers to defaults. |
| 25 | DGND | power_in | Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane. |
| 26 | SS_M/MP0 | bidirectional | SPI master slave select or multipurpose GPIO 0 with nominal 250 kΩ pull-up; at self boot, floating selects SPI and a 10 kΩ pull-down to DGND selects I2C. |
| 27 | MOSI_M/MP1 | bidirectional | SPI master data output or multipurpose GPIO 1 with disableable pull-up; disconnect when not in use. |
| 28 | SCL_M/SCLK_M/MP2 | bidirectional | I2C master serial clock (open collector, 2.0 kΩ pull-up to IOVDD), SPI master clock, or multipurpose GPIO 2. |
| 29 | SDA_M/MISO_M/MP3 | bidirectional | I2C master serial data (open collector, 2.0 kΩ pull-up to IOVDD), SPI master data input, or multipurpose GPIO 3. |
| 30 | MISO/SDA | bidirectional | SPI slave data output or I2C slave serial data (open collector, 2.0 kΩ pull-up to IOVDD); connect to IOVDD with 10.0 kΩ when unused. |
| 31 | SCLK/SCL | input | SPI slave serial clock or I2C slave serial clock input (2.0 kΩ pull-up to IOVDD for I2C); connect to IOVDD with 10.0 kΩ when unused. |
| 32 | MOSI/ADDR1 | input | SPI slave data input or I2C slave address MSB (ADDR1) with disableable pull-up. |
| 33 | SS/ADDR0 | input | SPI slave select or I2C slave address LSB (ADDR0) with nominal 250 kΩ pull-up. |
| 34 | SELFBOOT | input | Self boot select with pull-up; logic high (IOVDD) starts self boot from EEPROM on the next RESET rising edge, ground disables it. |
| 35 | DVDD | power_in | Digital supply, must be 1.2 V ± 5%, bypassed to Pin 36 (DGND). |
| 36 | DGND | power_in | Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane. |
| 37 | DGND | power_in | Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane. |
| 38 | IOVDD | power_in | Input/output supply, 1.8 V − 5% to 3.3 V + 10%, bypassed to Pin 37 (DGND). |
| 39 | LRCLK_OUT0/MP4 | bidirectional | Frame clock for Serial Output Port 0 (direction set by master/slave mode) or multipurpose GPIO 4. |
| 40 | BCLK_OUT0 | bidirectional | Bit clock for Serial Output Port 0, direction depending on master or slave mode. |
| 41 | SDATA_OUT0 | output | Serial Output Port 0 data (Channel 0 to 15), supporting 2-, 4-, 8- and 16-channel modes. |
| 42 | LRCLK_OUT1/MP5 | bidirectional | Frame clock for Serial Output Port 1 (direction set by master/slave mode) or multipurpose GPIO 5. |
| 43 | BCLK_OUT1 | bidirectional | Bit clock for Serial Output Port 1, direction depending on master or slave mode. |
| 44 | SDATA_OUT1 | output | Serial Output Port 1 data (Channel 16 to 31), supporting 2-, 4-, 8- and 16-channel modes. |
| 45 | MP6 | bidirectional | Configurable multipurpose general-purpose input/output 6. |
| 46 | MP7 | bidirectional | Configurable multipurpose general-purpose input/output 7. |
| 47 | LRCLK_OUT2/MP8 | bidirectional | Frame clock for Serial Output Port 2 (direction set by master/slave mode) or multipurpose GPIO 8. |
| 48 | BCLK_OUT2 | bidirectional | Bit clock for Serial Output Port 2, direction depending on master or slave mode. |
| 49 | SDATA_OUT2 | output | Serial Output Port 2 data (Channel 32 to 39), supporting 2-, 4-, 8-channel or flexible TDM mode. |
| 50 | LRCLK_OUT3/MP9 | bidirectional | Frame clock for Serial Output Port 3 (direction set by master/slave mode) or multipurpose GPIO 9. |
| 51 | BCLK_OUT3 | bidirectional | Bit clock for Serial Output Port 3, direction depending on master or slave mode. |
| 52 | SDATA_OUT3 | output | Serial Output Port 3 data (Channel 40 to 47), supporting 2-, 4-, 8-channel and flexible TDM modes. |
| 53 | DVDD | power_in | Digital supply, must be 1.2 V ± 5%, bypassed to Pin 54 (DGND). |
| 54 | DGND | power_in | Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane. |
| 55 | DGND | power_in | Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane. |
| 56 | IOVDD | power_in | Input/output supply, 1.8 V − 5% to 3.3 V + 10%, bypassed to Pin 55 (DGND). |
| 57 | BCLK_IN0 | bidirectional | Bit clock for Serial Input Port 0, direction depending on master or slave mode. |
| 58 | LRCLK_IN0/MP10 | bidirectional | Frame clock for Serial Input Port 0 (direction set by master/slave mode) or multipurpose GPIO 10. |
| 59 | SDATA_IN0 | input | Serial Input Port 0 data (Channel 0 to 15), supporting 2-, 4-, 8- or 16-channel mode. |
| 60 | BCLK_IN1 | bidirectional | Bit clock for Serial Input Port 1, direction depending on master or slave mode. |
| 61 | LRCLK_IN1/MP11 | bidirectional | Frame clock for Serial Input Port 1 (direction set by master/slave mode) or multipurpose GPIO 11. |
| 62 | SDATA_IN1 | input | Serial Input Port 1 data (Channel 16 to 31), supporting 2-, 4-, 8- or 16-channel mode. |
| 63 | THD_M | passive | Thermal diode negative input, connected to the D− pin of an external temperature sensor IC. |
| 64 | THD_P | passive | Thermal diode positive input, connected to the D+ pin of an external temperature sensor IC. |
| 65 | BCLK_IN2 | bidirectional | Bit clock for Serial Input Port 2, direction depending on master or slave mode. |
| 66 | LRCLK_IN2/MP12 | bidirectional | Frame clock for Serial Input Port 2 (direction set by master/slave mode) or multipurpose GPIO 12. |
| 67 | SDATA_IN2 | input | Serial Input Port 2 data (Channel 32 to 39), supporting 2-, 4-, 8-channel or flexible TDM mode. |
| 68 | BCLK_IN3 | bidirectional | Bit clock for Serial Input Port 3, direction depending on master or slave mode. |
| 69 | LRCLK_IN3/MP13 | bidirectional | Frame clock for Serial Input Port 3 (direction set by master/slave mode) or multipurpose GPIO 13. |
| 70 | SDATA_IN3 | input | Serial Input Port 3 data (Channel 40 to 47), supporting 2-, 4-, 8-channel or flexible TDM mode. |
| 71 | DVDD | power_in | Digital supply, must be 1.2 V ± 5%, bypassed to Pin 72 (DGND). |
| 72 | DGND | power_in | Digital and I/O ground reference; tie all DGND, AGND and PGND pins together in a common ground plane. |
| 73 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-72(10x10) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 73 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog Voltage | AVDD | 2.97 | 3.3 | 3.63 | V | Supply for analog circuitry, including auxiliary ADC | 6 |
| Digital Voltage | DVDD | 1.14 | 1.2 | 1.26 | V | Supply for digital circuitry, including the DSP core, ASRCs, and signal routing | 6 |
| PLL Voltage | PVDD | 2.97 | 3.3 | 3.63 | V | Supply for PLL circuitry | 6 |
| IOVDD Voltage | IOVDD | 1.71 | 3.3 | 3.63 | V | Supply for input/output circuitry, including pads and level shifters | 6 |
| Analog Current (AVDD) |  | 1.36 | 1.66 | 2 | mA |  | 6 |
| Analog Current Idle State |  | 1 | 1.1 | 40 | μA |  | 6 |
| Analog Current Reset State |  | 1 | 1.1 | 40 | μA |  | 6 |
| PLL Current (PVDD) |  | 8.3 | 10.2 | 15 | mA | 12.288 MHz master clock; default PLL settings | 6 |
| PLL Current Idle State |  | 18.4 | 18.7 | 40 | μA | Power applied, PLL not configured | 6 |
| PLL Current Reset State |  | 18.4 | 18.7 | 40 | μA | Power applied, RESET held low | 6 |
| I/O Current Power-Down State |  | 4.1 |  | 4.3 | mA | IOVDD = 1.8 V − 5% to 3.3 V + 10% | 6 |
| Digital Current Maximum Program, fCORE = 294.912 MHz |  |  | 485 | 920 | mA | ADAU1462 Operation State, fCORE = 294.912 MHz | 6 |
| Digital Current Typical Program, fCORE = 294.912 MHz |  |  | 330 |  | mA | Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active | 6 |
| Digital Current Minimal Program, fCORE = 294.912 MHz |  |  | 213 |  | mA | Test program includes 2-channel I/O, 10-band EQ per channel | 6 |
| Digital Current Idle State |  | 5.9 | 15.7 | 559 | mA | Power applied, DSP not enabled | 6 |
| Digital Current Reset State |  | 5.9 | 15.7 | 559 | mA | Power applied, RESET held low | 6 |
| ASRC I/O Sample Rate |  | 6 |  | 192 | kHz |  | 6 |
| ASRC Dynamic Range |  |  | 139 |  | dB | A-weighted, 20 Hz to 20 kHz | 6 |
| ASRC THD + N |  |  | -120 |  | dB |  | 6 |
| Crystal Oscillator Transconductance |  | 8.1 | 10.6 | 14.6 | mS |  | 6 |
| Regulator DVDD Voltage |  | 1.14 | 1.2 |  | V | Regulator maintains typical output voltage up to a maximum 800 mA load; IOVDD = 1.8 V − 5% to 3.3 V + 10% | 6 |
| Input High Level | VIH | 1.71 |  | 3.3 | V | IOVDD = 3.3 V | 7 |
| Input Low Level | VIL | 0 |  | 1.71 | V | IOVDD = 3.3 V | 7 |
| Input High Level | VIH | 0.92 |  | 1.8 | V | IOVDD = 1.8 V | 7 |
| Input Low Level | VIL | 0 |  | 0.89 | V | IOVDD = 1.8 V | 7 |
| Output High Level | VOH | 3.09 |  | 3.3 | V | IOVDD = 3.3 V, IOH = 1 mA | 7 |
| Output Low Level | VOL | 0 |  | 0.26 | V | IOVDD = 3.3 V, IOL = 1 mA | 7 |
| Output High Level | VOH | 1.45 |  | 1.8 | V | IOVDD = 1.8 V | 7 |
| Output Low Level | VOL | 0 |  | 0.33 | V | IOVDD = 1.8 V | 7 |
| Input Capacitance | CI |  |  | 2 | pF | Guaranteed by design | 7 |
| Auxiliary ADC Resolution |  |  | 10 |  | Bits |  | 8 |
| Auxiliary ADC Integrated Nonlinearity | INL | -2.5 |  | 2.5 | LSB |  | 8 |
| Auxiliary ADC Differential Nonlinearity | DNL | -2.5 |  | 2.5 | LSB |  | 8 |
| Auxiliary ADC Gain Error |  | -2.5 |  | 2.5 | LSB |  | 8 |
| Auxiliary ADC Input Impedance |  |  | 200 |  | kΩ |  | 8 |
| SCLK write frequency | fSCLKWRITE |  |  | 20 | MHz | SPI slave | 14 |
| SCLK read frequency | fSCLKREAD |  |  | 20 | MHz | SPI slave | 14 |
| SCLK pulse width low | tSCLKPWL | 6 |  |  | ns | SCLK = 20 MHz | 14 |
| SCLK pulse width high | tSCLKPWH | 21 |  |  | ns | SCLK = 20 MHz | 14 |
| MISO valid output delay | tMISOD |  |  | 39 | ns | from SCLK falling edge | 14 |
| SPI master clock frequency | fSCLK_M |  |  | 24 | MHz |  | 15 |
| PDM data setup time | tSETUP | 10 |  |  | ns |  | 16 |
| PDM data hold time | tHOLD | 5 |  |  | ns |  | 16 |
| DVDD to Ground |  | 0 |  | 1.4 | V |  | 17 |
| AVDD to Ground |  | 0 |  | 4 | V |  | 17 |
| IOVDD to Ground |  | 0 |  | 4 | V |  | 17 |
| PVDD to Ground |  | 0 |  | 4 | V |  | 17 |
| Maximum Ambient Temperature Range |  | -40 |  | 105 | °C |  | 17 |
| Maximum Junction Temperature |  |  |  | 125 | °C |  | 17 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 17 |
| Soldering |  |  |  | 300 | °C | 10 sec | 17 |
| Thermal coefficient ψJT | ψJT |  | 0.15 |  | °C/W | JEDEC 2s2p PCB, 25 thermal vias, natural convection | 17 |
| Thermal coefficient θJA | θJA |  | 29.15 |  | °C/W | JEDEC 2s2p PCB, 25 thermal vias, natural convection | 17 |
| Thermal coefficient θJB | θJB |  | 10.59 |  | °C/W | JEDEC 2s2p PCB, junction to board | 17 |
| Thermal coefficient θJCT | θJCT |  | 0.04 |  | °C/W | cold plate attached directly to exposed paddle | 17 |
| Thermal coefficient θJCB | θJCB |  | 3.39 |  | °C/W |  | 17 |

## CAD (KiCad official)

- Symbol: `ADAU1462WBCPZ300`
- Footprint: `Package_DFN_QFN:QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm`
- 3D model: LFCSP-72(10x10), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `adau1462wbcpz300-etched.step` / `adau1462wbcpz300-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adau1462wbcpz300.step` / `adau1462wbcpz300.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1462-1466.pdf) (202 pp, sha256 `c473f6316a5d3f95`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/adau1462wbcpz300-datasheet.pdf)

ADAU1462WBCPZ300

Verified ADAU1462WBCPZ300

Verification log 1 record

ADAU1462WBCPZ300

Pinout

Key specifications

Electrical characteristics

CAD (KiCad official)

Provenance