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ADAU1451WBCPZ

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Analog Devices Digital Signal Processors / Controllers (DSPs/DSCs), LFCSP-72(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ADAU1451WBCPZ

Analog Devices · Digital Signal Processors / Controllers (DSPs/DSCs) · LFCSP-72(10x10)

ADAU1451WBCPZ from Analog Devices, in a LFCSP-72(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DGND power_in Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
2 IOVDD power_in Input/output supply, 1.8 V −5% to 3.3 V +10%; bypass to pin 1 (DGND) with decoupling capacitors.
3 VDRIVE passive Base drive bias for an external PNP pass transistor of the digital supply regulator; connect to DGND or leave floating if DVDD is supplied externally.
4 SPDIFIN input Input to the integrated S/PDIF receiver, internally biased to IOVDD/2; leave floating when not in use and it draws approximately 0.1 mA when grounded.
5 SPDIFOUT output Configurable output from the integrated S/PDIF transmitter, internally biased to IOVDD/2; disconnect when not in use.
6 AGND power_in Analog ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
7 AVDD power_in Analog (auxiliary ADC) supply; must be 3.3 V ±10% and bypassed to pin 6 (AGND).
8 AUXADC0 input Auxiliary ADC input channel 0; full-scale is reached at AVDD and the pin may be left floating when not in use.
9 AUXADC1 input Auxiliary ADC input channel 1; full-scale is reached at AVDD and the pin may be left floating when not in use.
10 AUXADC2 input Auxiliary ADC input channel 2; full-scale is reached at AVDD and the pin may be left floating when not in use.
11 AUXADC3 input Auxiliary ADC input channel 3; full-scale is reached at AVDD and the pin may be left floating when not in use.
12 AUXADC4 input Auxiliary ADC input channel 4; full-scale is reached at AVDD and the pin may be left floating when not in use.
13 AUXADC5 input Auxiliary ADC input channel 5; full-scale is reached at AVDD and the pin may be left floating when not in use.
14 PGND power_in PLL ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
15 PVDD power_in PLL supply; must be 3.3 V ±10% and bypassed to pin 14 (PGND).
16 PLLFILT passive PLL filter node whose internally generated voltage is typically between 1.65 V and 2.10 V.
17 DGND power_in Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
18 IOVDD power_in Input/output supply, 1.8 V −5% to 3.3 V +10%; bypass to pin 17 (DGND) with decoupling capacitors.
19 DGND power_in Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
20 DVDD power_in Digital supply; must be 1.2 V ±5%, supplied externally or by the internal regulator with an external pass transistor, and bypassed to pin 19 (DGND).
21 XTALIN/MCLK input Crystal oscillator input or master clock input to the PLL; can be driven directly or used with a crystal between pins 21 and 22.
22 XTALOUT output Crystal oscillator output for driving an external crystal; disconnect when not in use.
23 CLKOUT output Configurable master clock output that can be set to 1x, 2x, 4x, or 8x the divided PLL input clock; disconnect when not in use.
24 RESET input Active-low reset input; a reset is triggered on a high-to-low edge and exited on a low-to-high edge, setting all RAMs and registers to default values.
25 DGND power_in Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
26 SS_M/MP0 bidirectional SPI master slave select (SS_M) or multipurpose GPIO MP0; has a nominal 250 kΩ internal pull-up and selects self-boot protocol when SELFBOOT is high at reset.
27 MOSI_M/MP1 output SPI master data output (MOSI_M) or multipurpose GPIO MP1 with an internal pull-up; disconnect when not in use.
28 SCL_M/SCLK_M/MP2 bidirectional I2C master serial clock (open collector, requires pull-up to IOVDD), SPI master clock, or multipurpose GPIO MP2; disconnect when not in use.
29 SDA_M/MISO_M/MP3 bidirectional I2C master serial data (open collector, requires pull-up to IOVDD), SPI master data input, or multipurpose GPIO MP3; disconnect when not in use.
30 MISO/SDA bidirectional SPI slave data output or I2C slave serial data (open collector, requires pull-up to IOVDD); connect to IOVDD with 10.0 kΩ when not in use.
31 SCLK/SCL input SPI slave serial clock or I2C slave serial clock; I2C requires a pull-up to IOVDD and 10.0 kΩ to IOVDD when not in use.
32 MOSI/ADDR1 input SPI slave data input or I2C slave address bit 2 (ADDR1), which must be hardwired to IOVDD or GND.
33 SS/ADDR0 input SPI slave select or I2C slave address bit 1 (ADDR0), which must be hardwired to IOVDD or GND.
34 SELFBOOT input Self boot select; connecting to IOVDD initiates self boot on the next rising edge of RESET, while ground disables it, and it may be tied directly or through a 1.0 kΩ or larger resistor.
35 DVDD power_in Digital supply; must be 1.2 V ±5%, supplied externally or by the internal regulator, and bypassed to pin 36 (DGND).
36 DGND power_in Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
37 DGND power_in Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
38 IOVDD power_in Input/output supply, 1.8 V −5% to 3.3 V +10%; bypass to pin 37 (DGND) with decoupling capacitors.
39 LRCLK_OUT0/MP4 bidirectional Serial output port 0 frame clock (master or slave direction) or multipurpose GPIO MP4; disconnect when not in use.
40 BCLK_OUT0 bidirectional Serial output port 0 bit clock, bidirectional depending on master or slave operation; disconnect when not in use.
41 SDATA_OUT0 output Serial data output port 0 carrying channels 0 to 15 in 2-, 4-, 8-, or 16-channel modes; disconnect when not in use.
42 LRCLK_OUT1/MP5 bidirectional Serial output port 1 frame clock (master or slave direction) or multipurpose GPIO MP5; disconnect when not in use.
43 BCLK_OUT1 bidirectional Serial output port 1 bit clock, bidirectional depending on master or slave operation; disconnect when not in use.
44 SDATA_OUT1 output Serial data output port 1 carrying channels 16 to 31 in 2-, 4-, 8-, or 16-channel modes; disconnect when not in use.
45 MP6 bidirectional Configurable multipurpose GPIO 6; disconnect when not in use.
46 MP7 bidirectional Configurable multipurpose GPIO 7; disconnect when not in use.
47 LRCLK_OUT2/MP8 bidirectional Serial output port 2 frame clock (master or slave direction) or multipurpose GPIO MP8; disconnect when not in use.
48 BCLK_OUT2 bidirectional Serial output port 2 bit clock, bidirectional depending on master or slave operation; disconnect when not in use.
49 SDATA_OUT2 output Serial data output port 2 carrying channels 32 to 39 in 2-, 4-, 8-channel or flexible TDM modes; disconnect when not in use.
50 LRCLK_OUT3/MP9 bidirectional Serial output port 3 frame clock (master or slave direction) or multipurpose GPIO MP9; disconnect when not in use.
51 BCLK_OUT3 bidirectional Serial output port 3 bit clock, bidirectional depending on master or slave operation; disconnect when not in use.
52 SDATA_OUT3 output Serial data output port 3 carrying channels 40 to 47 in 2-, 4-, 8-channel or flexible TDM modes; disconnect when not in use.
53 DVDD power_in Digital supply; must be 1.2 V ±5%, supplied externally or by the internal regulator, and bypassed to pin 54 (DGND).
54 DGND power_in Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
55 DGND power_in Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
56 IOVDD power_in Input/output supply, 1.8 V −5% to 3.3 V +10%; bypass to pin 55 (DGND) with decoupling capacitors.
57 BCLK_IN0 bidirectional Serial input port 0 bit clock, bidirectional depending on master or slave operation; disconnect when not in use.
58 LRCLK_IN0/MP10 bidirectional Serial input port 0 frame clock (master or slave direction) or multipurpose GPIO MP10; disconnect when not in use.
59 SDATA_IN0 input Serial data input port 0 carrying channels 0 to 15 in 2-, 4-, 8-, or 16-channel modes; disconnect when not in use.
60 BCLK_IN1 bidirectional Serial input port 1 bit clock, bidirectional depending on master or slave operation; disconnect when not in use.
61 LRCLK_IN1/MP11 bidirectional Serial input port 1 frame clock (master or slave direction) or multipurpose GPIO MP11; disconnect when not in use.
62 SDATA_IN1 input Serial data input port 1 carrying channels 16 to 31 in 2-, 4-, 8-, or 16-channel modes; disconnect when not in use.
63 THD_M passive Thermal diode negative input; connect to the D− pin of an external temperature sensor IC, or disconnect when not in use.
64 THD_P passive Thermal diode positive input; connect to the D+ pin of an external temperature sensor IC, or disconnect when not in use.
65 BCLK_IN2 bidirectional Serial input port 2 bit clock, bidirectional depending on master or slave operation; disconnect when not in use.
66 LRCLK_IN2/MP12 bidirectional Serial input port 2 frame clock (master or slave direction) or multipurpose GPIO MP12; disconnect when not in use.
67 SDATA_IN2 input Serial data input port 2 carrying channels 32 to 39 in 2-, 4-, 8-channel or flexible TDM modes; disconnect when not in use.
68 BCLK_IN3 bidirectional Serial input port 3 bit clock, bidirectional depending on master or slave operation; disconnect when not in use.
69 LRCLK_IN3/MP13 bidirectional Serial input port 3 frame clock (master or slave direction) or multipurpose GPIO MP13; disconnect when not in use.
70 SDATA_IN3 input Serial data input port 3 carrying channels 40 to 47 in 2-, 4-, 8-channel or flexible TDM modes; disconnect when not in use.
71 DVDD power_in Digital supply; must be 1.2 V ±5%, supplied externally or by the internal regulator, and bypassed to pin 72 (DGND).
72 DGND power_in Digital and I/O ground reference; tie all DGND, AGND, and PGND pins directly together in a common ground plane.
73 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-72(10x10)
Category Single Chip Microcomputer/Microcontroller
Pins 73

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog Voltage (AVDD Pin) AVDD 2.97 3.3 3.63 V Supply for analog circuitry, including auxiliary ADC 9
Digital Voltage (DVDD Pin) DVDD 1.14 1.2 1.26 V Supply for digital circuitry, including the DSP core, ASRCs, and signal routing 9
PLL Voltage (PVDD Pin) PVDD 2.97 3.3 3.63 V Supply for PLL circuitry 9
IOVDD Voltage (IOVDD Pin) IOVDD 1.71 3.3 3.63 V Supply for input/output circuitry, including pads and level shifters 9
Analog Current (AVDD Pin) IAVDD 1.44 1.72 2 mA 9
Analog Current Idle State IAVDD 0 6.3 40 µA 9
Analog Current Reset State IAVDD 0.26 7.1 40 µA 9
PLL Current (PVDD Pin) IPVDD 6 10.9 15 mA 12.288 MHz master clock; default PLL settings 9
PLL Current Idle State IPVDD 0 7.8 40 µA Power applied, PLL not configured 9
PLL Current Reset State IPVDD 1.2 9.3 40 µA Power applied, RESET held low 9
I/O Current Power-Down State IIOVDD 1.3 2.2 mA IOVDD = 1.8 V − 5% to 3.3 V + 10% 9
Digital Current Maximum Program, ADAU1451 IDVDD 500 690 mA TA = −40°C to +105°C 9
Digital Current Idle State, ADAU1451 family IDVDD 315 635 mA 10
Digital Current Reset State, ADAU1451 family IDVDD 315 635 mA 10
Crystal Oscillator Transconductance gm 8.1 10.6 14.6 mS 10
DVDD Regulator Voltage DVDD 1.14 1.2 V Regulator maintains typical output voltage up to a maximum 800 mA load; IOVDD = 1.8 V − 5% to 3.3 V + 10% 10
DVDD Regulator Maximum Output Voltage DVDD 1.26 V Regulator maximum output voltage with a minimum 1 mA load; IOVDD = 1.8 V − 5% to 3.3 V + 10% 10
Digital Current Typical Program, ADAU1451 IDVDD 200 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active 9
Digital Current Minimal Program, ADAU1451 IDVDD 160 mA Test program includes 2-channel I/O, 10-band EQ per channel 9
Digital Input Leakage High Level, pull-up IIH -2 2 µA Digital input pins with pull-up resistor 11
Digital Input Leakage High Level, pull-down IIH 2 12 µA Digital input pins with pull-down resistor 11
Digital Input Leakage High Level, no pull IIH -2 2 µA Digital input pins with no pull resistor 11
Digital Input Leakage High Level, MCLK IIH 0 8 µA MCLK 11
Digital Input Leakage High Level, SPDIFIN IIH 80 120 µA SPDIFIN 11
Digital Input Leakage Low Level, pull-up IIL -12 -2 µA Digital input pins with pull-up resistor; at 0 V 11
Digital Input Leakage Low Level, pull-down IIL -2 2 µA Digital input pins with pull-down resistor; at 0 V 11
Digital Input Leakage Low Level, no pull IIL -2 2 µA Digital input pins with no pull resistor; at 0 V 11
Digital Input Leakage Low Level, MCLK IIL -8 0 µA MCLK; at 0 V 11
Digital Input Leakage Low Level, SPDIFIN IIL -120 -77 µA SPDIFIN; at 0 V 11
Integrated Nonlinearity (Aux ADC) INL -2 2 LSB Auxiliary ADC; TA = −40°C to +105°C 12
Differential Nonlinearity (Aux ADC) DNL -2 2 LSB Auxiliary ADC; TA = −40°C to +105°C 12
Gain Error (Aux ADC) -2 2 LSB Auxiliary ADC; TA = −40°C to +105°C 12
MCLK Frequency fMCLK 2.375 36 MHz MCLK frequency 12
MCLK Period tMCLK 27.8 421 ns MCLK period 12
MCLK Duty Cycle tMCLKD 25 75 % MCLK duty cycle 12
CLKOUT Jitter 12 106 ps Cycle-to-cycle rms average 12
Core Clock Frequency, ADAU1451 fCORE 152 294.912 MHz System (DSP core) clock frequency; PLL feedback divider ranges from 64 to 108 12
Analog Voltage (AVDD Pin) Absolute Maximum AVDD 0 4 V AVDD to Ground 21
Digital Voltage (DVDD Pin) Absolute Maximum DVDD 0 1.4 V DVDD to Ground 21
IOVDD Absolute Maximum IOVDD 0 4 V IOVDD to Ground 21
PVDD Absolute Maximum PVDD 0 4 V PVDD to Ground 21
Maximum Junction Temperature TJ 125 °C 21
Storage Temperature Range TSTG -65 150 °C 21
Soldering Temperature 300 °C 10 sec 21
Maximum Ambient Temperature Range, W Grade TA -40 105 °C W grade 21
Thermal Resistance Junction-to-Ambient θJA 23.38 °C/W 72-Lead LFCSP; 4-layer JEDEC board 21
Thermal Resistance Junction-to-Case θJC 3.3 °C/W 72-Lead LFCSP; 4-layer JEDEC board 21

CAD (KiCad official)

  • Symbol: ADAU1451WBCPZ
  • Footprint: Package_DFN_QFN:QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-72(10x10) (KiCad packages3D, STEP)
  • 3D model files: adau1451wbcpz-etched.step / adau1451wbcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adau1451wbcpz.step / adau1451wbcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (195 pp, sha256 100f2df879403c09, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF