component
ADAU1372BCPZ
Public Made by Adomby adom
Analog Devices Interface - Specialized, LFCSP-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADAU1372BCPZ
Analog Devices · Interface - Specialized · LFCSP-40(6x6)
ADAU1372BCPZ from Analog Devices, in a LFCSP-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SDA/MISO | bidirectional | I2C data (SDA) is a bidirectional open-collector that must have a 2.0 kΩ pull-up resistor; in SPI mode it is the MISO data output, tristated when no SPI read is active. |
| 2 | SCL/SCLK | input | I2C clock (SCL) is an open-collector input requiring a 2.0 kΩ pull-up in I2C mode; in SPI mode it is the SCLK input, which may run continuously or be gated off between transactions. |
| 3 | ADDR1/MOSI | input | In I2C mode this pin is address bit 1 (ADDR1); in SPI mode it is the MOSI serial data input. |
| 4 | ADDR0/SS | input | In I2C mode this pin is address bit 0 (ADDR0); in SPI mode it is the SS latch signal, which must go low at the start and high at the end of each transaction. |
| 5 | DGND | power_in | Digital ground; tie AGND and DGND directly together in a common ground plane. |
| 6 | MICBIAS0 | output | Bias voltage for electret microphone; decouple with a 1 µF capacitor. |
| 7 | MICBIAS1 | output | Bias voltage for electret microphone; decouple with a 1 µF capacitor. |
| 8 | AIN0REF | input | ADC0 input reference; AC couple this pin to ground with a 10 µF capacitor. |
| 9 | AIN0 | input | ADC0 analog input. |
| 10 | AVDD | power_in | 1.8 V to 3.3 V analog supply; decouple to AGND with a 0.1 µF capacitor. |
| 11 | AGND | power_in | Analog ground; tie AGND and DGND directly together and decouple AGND to AVDD with a 0.1 µF capacitor. |
| 12 | CM | output | AVDD/2 common-mode reference; connect a 10 µF to 47 µF decoupling capacitor to ground to reduce crosstalk between ADCs and DACs. |
| 13 | AIN1REF | input | ADC1 input reference; AC couple this pin to ground with a 10 µF capacitor. |
| 14 | AIN1 | input | ADC1 analog input. |
| 15 | AIN2REF | input | ADC2 input reference; AC couple this pin to ground with a 10 µF capacitor. |
| 16 | AIN2 | input | ADC2 analog input. |
| 17 | AIN3REF | input | ADC3 input reference; AC couple this pin to ground with a 10 µF capacitor. |
| 18 | AIN3 | input | ADC3 analog input. |
| 19 | AVDD | power_in | 1.8 V to 3.3 V analog supply; decouple to AGND with a 0.1 µF capacitor. |
| 20 | AGND | power_in | Analog ground; see the Grounding section. |
| 21 | HPOUTLN/LOUTLN | output | Left headphone inverted output (HPOUTLN) or left line output inverted (LOUTLN). |
| 22 | HPOUTLP/LOUTLP | output | Left headphone noninverted output (HPOUTLP) or noninverted single-ended left line output (LOUTLP). |
| 23 | AGND | power_in | Headphone amplifier ground; see the Grounding section. |
| 24 | AVDD | power_in | Headphone amplifier power, 1.8 V to 3.3 V analog supply; decouple to AGND with a 0.1 µF capacitor; the PCB trace must supply the higher headphone drive current. |
| 25 | HPOUTRN/LOUTRN | output | Right headphone inverted output (HPOUTRN) or right line output inverted (LOUTRN). |
| 26 | HPOUTRP/LOUTRP | output | Right headphone noninverted output (HPOUTRP) or noninverted single-ended right line output (LOUTRP). |
| 27 | PD | input | Active low power-down; all digital and analog circuits are powered down when low, and an internal pull-down holds the device in power-down if the input floats. |
| 28 | REG_OUT | output | Regulator output voltage; connect to DVDD if the internal voltage regulator generates the DVDD voltage. |
| 29 | DVDD | power_in | Digital core supply, generated by an on-board regulator or supplied externally; decouple to DGND with a 0.1 µF capacitor. |
| 30 | DGND | power_in | Digital ground; see the Grounding section. |
| 31 | LRCLK | bidirectional | Serial data port frame clock. |
| 32 | BCLK | bidirectional | Serial data port bit clock. |
| 33 | DAC_SDATA/MP0 | bidirectional | DAC serial input data (DAC_SDATA) or general-purpose input MP0. |
| 34 | ADC_SDATA0/MP1 | bidirectional | ADC serial data output 0 (ADC_SDATA0) or general-purpose input MP1. |
| 35 | ADC_SDATA1/CLKOUT/MP6 | bidirectional | ADC serial data output 1 (ADC_SDATA1), master clock output or digital microphone clock (CLKOUT), or general-purpose input MP6; CLKOUT disables ADC_SDATA1. |
| 36 | DMIC2_3/MP5 | input | Digital microphone stereo input 2 and 3 (DMIC2_3) or general-purpose input MP5. |
| 37 | DMIC0_1/MP4 | input | Digital microphone stereo input 0 and 1 (DMIC0_1) or general-purpose input MP4. |
| 38 | XTALO | output | Crystal clock output of the crystal amplifier; must not be used to clock other ICs, and CLKOUT (pin 35) should be used for a master clock output. |
| 39 | XTALI/MCLKIN | input | Crystal clock input (XTALI) or master clock input (MCLKIN). |
| 40 | IOVDD | power_in | Supply for digital input and output pins; it sets the highest input voltage allowed on the digital inputs and should be decoupled to DGND with a 0.1 µF capacitor. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-40(6x6) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 41 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supplies (AVDD, IOVDD) | -0.3 | 3.63 | V | 13 | |||
| Digital Supply (DVDD) | -0.3 | 1.98 | V | 13 | |||
| Input Current (Except Supply Pins) | -20 | 20 | mA | Except supply pins | 13 | ||
| Analog Input Voltage (Signal Pins) | -0.3 | V | Upper limit printed as AVDD + 0.3 V | 13 | |||
| Digital Input Voltage (Signal Pins) | -0.3 | V | Upper limit printed as IOVDD + 0.3 V | 13 | |||
| Operating Temperature Range (Case) | -40 | 85 | °C | Case | 13 | ||
| Storage Temperature Range | -65 | 150 | °C | 13 | |||
| MCLKIN period | tMP | 37 | 125 | ns | 8 MHz to 27 MHz input clock using PLL | 10 | |
| Internal MCLK period | tMCLK | 77 | 82 | ns | Direct MCLK and PLL output divided by 2 | 10 | |
| ADC_SDATAx delay | tSOD | 0 | 34 | ns | Time from BCLK falling (master and slave modes) | 10 | |
| Junction-to-ambient thermal resistance | θJA | 29 | °C/W | 40-Lead LFCSP; 4-layer JEDEC PCB, exposed pad soldered | 13 | ||
| Junction-to-case thermal resistance | θJC | 1.8 | °C/W | 40-Lead LFCSP; simulated at exposed pad | 13 |
CAD (KiCad official)
- Symbol:
ADAU1372BCPZ - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: LFCSP-40(6x6) (KiCad packages3D, STEP)
- 3D model files:
adau1372bcpz-etched.step/adau1372bcpz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adau1372bcpz.step/adau1372bcpz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (92 pp, sha256
62817974e09f266d, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADAU1372BCPZ
**Analog Devices** · Interface - Specialized · LFCSP-40(6x6)
ADAU1372BCPZ from Analog Devices, in a LFCSP-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SDA/MISO | bidirectional | I2C data (SDA) is a bidirectional open-collector that must have a 2.0 kΩ pull-up resistor; in SPI mode it is the MISO data output, tristated when no SPI read is active. |
| 2 | SCL/SCLK | input | I2C clock (SCL) is an open-collector input requiring a 2.0 kΩ pull-up in I2C mode; in SPI mode it is the SCLK input, which may run continuously or be gated off between transactions. |
| 3 | ADDR1/MOSI | input | In I2C mode this pin is address bit 1 (ADDR1); in SPI mode it is the MOSI serial data input. |
| 4 | ADDR0/SS | input | In I2C mode this pin is address bit 0 (ADDR0); in SPI mode it is the SS latch signal, which must go low at the start and high at the end of each transaction. |
| 5 | DGND | power_in | Digital ground; tie AGND and DGND directly together in a common ground plane. |
| 6 | MICBIAS0 | output | Bias voltage for electret microphone; decouple with a 1 µF capacitor. |
| 7 | MICBIAS1 | output | Bias voltage for electret microphone; decouple with a 1 µF capacitor. |
| 8 | AIN0REF | input | ADC0 input reference; AC couple this pin to ground with a 10 µF capacitor. |
| 9 | AIN0 | input | ADC0 analog input. |
| 10 | AVDD | power_in | 1.8 V to 3.3 V analog supply; decouple to AGND with a 0.1 µF capacitor. |
| 11 | AGND | power_in | Analog ground; tie AGND and DGND directly together and decouple AGND to AVDD with a 0.1 µF capacitor. |
| 12 | CM | output | AVDD/2 common-mode reference; connect a 10 µF to 47 µF decoupling capacitor to ground to reduce crosstalk between ADCs and DACs. |
| 13 | AIN1REF | input | ADC1 input reference; AC couple this pin to ground with a 10 µF capacitor. |
| 14 | AIN1 | input | ADC1 analog input. |
| 15 | AIN2REF | input | ADC2 input reference; AC couple this pin to ground with a 10 µF capacitor. |
| 16 | AIN2 | input | ADC2 analog input. |
| 17 | AIN3REF | input | ADC3 input reference; AC couple this pin to ground with a 10 µF capacitor. |
| 18 | AIN3 | input | ADC3 analog input. |
| 19 | AVDD | power_in | 1.8 V to 3.3 V analog supply; decouple to AGND with a 0.1 µF capacitor. |
| 20 | AGND | power_in | Analog ground; see the Grounding section. |
| 21 | HPOUTLN/LOUTLN | output | Left headphone inverted output (HPOUTLN) or left line output inverted (LOUTLN). |
| 22 | HPOUTLP/LOUTLP | output | Left headphone noninverted output (HPOUTLP) or noninverted single-ended left line output (LOUTLP). |
| 23 | AGND | power_in | Headphone amplifier ground; see the Grounding section. |
| 24 | AVDD | power_in | Headphone amplifier power, 1.8 V to 3.3 V analog supply; decouple to AGND with a 0.1 µF capacitor; the PCB trace must supply the higher headphone drive current. |
| 25 | HPOUTRN/LOUTRN | output | Right headphone inverted output (HPOUTRN) or right line output inverted (LOUTRN). |
| 26 | HPOUTRP/LOUTRP | output | Right headphone noninverted output (HPOUTRP) or noninverted single-ended right line output (LOUTRP). |
| 27 | PD | input | Active low power-down; all digital and analog circuits are powered down when low, and an internal pull-down holds the device in power-down if the input floats. |
| 28 | REG_OUT | output | Regulator output voltage; connect to DVDD if the internal voltage regulator generates the DVDD voltage. |
| 29 | DVDD | power_in | Digital core supply, generated by an on-board regulator or supplied externally; decouple to DGND with a 0.1 µF capacitor. |
| 30 | DGND | power_in | Digital ground; see the Grounding section. |
| 31 | LRCLK | bidirectional | Serial data port frame clock. |
| 32 | BCLK | bidirectional | Serial data port bit clock. |
| 33 | DAC_SDATA/MP0 | bidirectional | DAC serial input data (DAC_SDATA) or general-purpose input MP0. |
| 34 | ADC_SDATA0/MP1 | bidirectional | ADC serial data output 0 (ADC_SDATA0) or general-purpose input MP1. |
| 35 | ADC_SDATA1/CLKOUT/MP6 | bidirectional | ADC serial data output 1 (ADC_SDATA1), master clock output or digital microphone clock (CLKOUT), or general-purpose input MP6; CLKOUT disables ADC_SDATA1. |
| 36 | DMIC2_3/MP5 | input | Digital microphone stereo input 2 and 3 (DMIC2_3) or general-purpose input MP5. |
| 37 | DMIC0_1/MP4 | input | Digital microphone stereo input 0 and 1 (DMIC0_1) or general-purpose input MP4. |
| 38 | XTALO | output | Crystal clock output of the crystal amplifier; must not be used to clock other ICs, and CLKOUT (pin 35) should be used for a master clock output. |
| 39 | XTALI/MCLKIN | input | Crystal clock input (XTALI) or master clock input (MCLKIN). |
| 40 | IOVDD | power_in | Supply for digital input and output pins; it sets the highest input voltage allowed on the digital inputs and should be decoupled to DGND with a 0.1 µF capacitor. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-40(6x6) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 41 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supplies (AVDD, IOVDD) | | -0.3 | | 3.63 | V | | 13 |
| Digital Supply (DVDD) | | -0.3 | | 1.98 | V | | 13 |
| Input Current (Except Supply Pins) | | -20 | | 20 | mA | Except supply pins | 13 |
| Analog Input Voltage (Signal Pins) | | -0.3 | | | V | Upper limit printed as AVDD + 0.3 V | 13 |
| Digital Input Voltage (Signal Pins) | | -0.3 | | | V | Upper limit printed as IOVDD + 0.3 V | 13 |
| Operating Temperature Range (Case) | | -40 | | 85 | °C | Case | 13 |
| Storage Temperature Range | | -65 | | 150 | °C | | 13 |
| MCLKIN period | tMP | 37 | | 125 | ns | 8 MHz to 27 MHz input clock using PLL | 10 |
| Internal MCLK period | tMCLK | 77 | | 82 | ns | Direct MCLK and PLL output divided by 2 | 10 |
| ADC_SDATAx delay | tSOD | 0 | | 34 | ns | Time from BCLK falling (master and slave modes) | 10 |
| Junction-to-ambient thermal resistance | θJA | | 29 | | °C/W | 40-Lead LFCSP; 4-layer JEDEC PCB, exposed pad soldered | 13 |
| Junction-to-case thermal resistance | θJC | | 1.8 | | °C/W | 40-Lead LFCSP; simulated at exposed pad | 13 |
## CAD (KiCad official)
- Symbol: `ADAU1372BCPZ`
- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`
- 3D model: LFCSP-40(6x6) (KiCad packages3D, STEP)
- 3D model files: `adau1372bcpz-etched.step` / `adau1372bcpz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adau1372bcpz.step` / `adau1372bcpz.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1372.pdf) (92 pp, sha256 `62817974e09f266d`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/adau1372bcpz-datasheet.pdf)