component
ADAS1000-4BSTZ
Public Made by Adomby adom
Analog Devices Pre-ordered Chips, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADAS1000-4BSTZ
Analog Devices · Pre-ordered Chips · LQFP-64(10x10)
ADAS1000-4BSTZ from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 18 | AVDD | power_in | Analog supply, to be decoupled per the Power Supply, Grounding, and Decoupling Strategy section. |
| 23 | AVDD | power_in | Analog supply, to be decoupled per the Power Supply, Grounding, and Decoupling Strategy section. |
| 58 | AVDD | power_in | Analog supply, to be decoupled per the Power Supply, Grounding, and Decoupling Strategy section. |
| 63 | AVDD | power_in | Analog supply, to be decoupled per the Power Supply, Grounding, and Decoupling Strategy section. |
| 35 | IOVDD | power_in | Digital supply for digital input/output voltage levels, with bypass capacitors as recommended in the datasheet. |
| 46 | IOVDD | power_in | Digital supply for digital input/output voltage levels, with bypass capacitors as recommended in the datasheet. |
| 26 | ADCVDD | power_in | Analog supply for the ADC from an on-chip regulator, mainly for decoupling; may be externally supplied at 1.8 V with VREG_EN tied to ground, and must not supply other functions. |
| 55 | ADCVDD | power_in | Analog supply for the ADC from an on-chip regulator, mainly for decoupling; may be externally supplied at 1.8 V with VREG_EN tied to ground, and must not supply other functions. |
| 30 | DVDD | power_in | Digital core supply from an on-chip regulator, mainly for decoupling; may be overdriven by an external 1.8 V supply with VREG_EN tied to ground. |
| 51 | DVDD | power_in | Digital core supply from an on-chip regulator, mainly for decoupling; may be overdriven by an external 1.8 V supply with VREG_EN tied to ground. |
| 2 | AGND | power_in | Analog ground. |
| 15 | AGND | power_in | Analog ground. |
| 24 | AGND | power_in | Analog ground. |
| 25 | AGND | power_in | Analog ground. |
| 56 | AGND | power_in | Analog ground. |
| 57 | AGND | power_in | Analog ground. |
| 31 | DGND | power_in | Digital ground. |
| 34 | DGND | power_in | Digital ground. |
| 40 | DGND | power_in | Digital ground. |
| 47 | DGND | power_in | Digital ground. |
| 50 | DGND | power_in | Digital ground. |
| 59 | VREG_EN | input | Enables or disables the internal ADCVDD and DVDD regulators; tie to AVDD to enable or to ground to disable. |
| 10 | ECG1_LA | input | Analog input, Left Arm (LA). |
| 11 | ECG2_LL | input | Analog input, Left Leg (LL). |
| 12 | ECG3_RA | input | Analog input, Right Arm (RA). |
| 4 | EXT_RESP_RA | input | Optional external respiration input. |
| 5 | EXT_RESP_LL | input | Optional external respiration input. |
| 6 | EXT_RESP_LA | input | Optional external respiration input. |
| 62 | RESPDAC_LL | output | Optional path for higher performance respiration resolution, respiration DAC drive, negative side 0. |
| 60 | SHIELD/RESPDAC_LA | output | User-configured shared pin: shield driver output (SHIELD) or respiration DAC drive negative side 1 (RESPDAC_LA). |
| 3 | RESPDAC_RA | output | Optional path for higher performance respiration resolution, respiration DAC drive, positive side. |
| 22 | CM_OUT/WCT | output | Common-mode output voltage (average of selected electrodes); not intended to drive current. |
| 19 | CM_IN | input | Common-mode input. |
| 21 | RLD_SJ | passive | Summing junction for the right leg drive amplifier. |
| 20 | RLD_OUT | output | Output and feedback junction for the right leg drive amplifier. |
| 61 | CAL_DAC_IO | bidirectional | Calibration DAC input/output: output for a primary device, input for a secondary device; not intended to drive current. |
| 9 | REFIN | input | Reference input; in standalone mode connect REFOUT to REFIN, with 10 μF (ESR < 0.2 Ω) in parallel with 0.1 μF bypass capacitors to GND close to the pin. |
| 8 | REFOUT | output | Reference output. |
| 7 | REFGND | power_in | Reference ground; connect to a clean ground. |
| 27 | XTAL1 | passive | External crystal connects between XTAL1 and XTAL2, each requiring a 15 pF capacitor to ground. |
| 28 | XTAL2 | passive | External crystal connects between XTAL1 and XTAL2, each requiring a 15 pF capacitor to ground. |
| 29 | CLK_IO | bidirectional | Buffered clock input/output: output for a primary device, input for a secondary device; powers up in high impedance. |
| 41 | CS | input | Chip select and frame sync, active low; can frame each word or the entire suite of data in framing mode. |
| 44 | SCLK | input | Serial clock input; data is clocked in on a rising edge and out on a falling edge. |
| 43 | SDI | input | Serial data input. |
| 53 | PD | input | Power-down, active low. |
| 45 | SDO | output | Serial data output for reading back register configuration data and for the data frames. |
| 42 | DRDY | output | Digital output indicating conversion data is ready when low and busy when high; the entire packet must be read for DRDY to return high. |
| 54 | RESET | input | Digital input with internal pull-up resistor that resets all internal nodes to their power-on reset values. |
| 52 | SYNC_GANG | bidirectional | Digital input/output for synchronization of ganged devices (output on primary, input on secondary); powers up in high impedance. |
| 36 | GPIO0/MCS | bidirectional | General-purpose I/O or primary 128 kHz SPI CS. |
| 37 | GPIO1/MSCLK | bidirectional | General-purpose I/O or primary 128 kHz SPI SCLK. |
| 38 | GPIO2/MSDO | bidirectional | General-purpose I/O or primary 128 kHz SPI SDO. |
| 39 | GPIO3 | bidirectional | General-purpose I/O. |
| 1 | NC | unconnected | No connect; do not connect to this pin. |
| 13 | NC | unconnected | No connect; do not connect to this pin. |
| 14 | NC | unconnected | No connect; do not connect to this pin. |
| 16 | NC | unconnected | No connect; do not connect to this pin. |
| 17 | NC | unconnected | No connect; do not connect to this pin. |
| 32 | NC | unconnected | No connect; do not connect to this pin. |
| 33 | NC | unconnected | No connect; do not connect to this pin. |
| 48 | NC | unconnected | No connect; do not connect to this pin. |
| 49 | NC | unconnected | No connect; do not connect to this pin. |
| 64 | NC | unconnected | No connect; do not connect to this pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LQFP-64(10x10) |
| Category | Interface ICs |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Electrode Input Range GAIN 0 | 0.3 | 1.3 | 2.3 | V | GAIN 0 (gain setting ×1.4) | 4 | |
| Electrode Input Range GAIN 1 | 0.63 | 1.3 | 1.97 | V | GAIN 1 (gain setting ×2.1) | 4 | |
| Electrode Input Range GAIN 2 | 0.8 | 1.3 | 1.8 | V | GAIN 2 (gain setting ×2.8) | 4 | |
| Electrode Input Range GAIN 3 | 0.97 | 1.3 | 1.63 | V | GAIN 3 (gain setting ×4.2) | 4 | |
| Input Bias Current | -40 | 1 | 40 | nA | Each electrode input; over operating range; dc and ac lead-off are disabled | 4 | |
| Input Bias Current (AGND to AVDD) | -200 | 200 | nA | AGND to AVDD | 4 | ||
| CMRR | CMRR | 105 | 110 | dB | 51 kΩ imbalance, 60 Hz with ±300 mV differential dc offset; with driven leg loop closed | 4 | |
| Gain Error GAIN 0 to GAIN 2 | -1 | 0.01 | 1 | % | GAIN 0 to GAIN 2, factory calibrated | 5 | |
| Gain Error GAIN 3 | -2 | 0.1 | 2 | % | GAIN 3 setting, no factory calibration | 5 | |
| Gain Matching GAIN 0 to GAIN 2 | -0.1 | 0.02 | 0.1 | % | GAIN 0 to GAIN 2 | 5 | |
| Gain Matching GAIN 3 | -0.5 | 0.1 | 0.5 | % | GAIN 3 | 5 | |
| Gain Tempco | 25 | ppm/°C | 5 | ||||
| Common-Mode Input Voltage Range | 0.3 | 2.3 | V | CM_IN pin | 5 | ||
| CM_IN Input Bias Current | -40 | 1 | 40 | nA | Over operating range; dc and ac lead-off disabled | 5 | |
| CM_IN Input Bias Current (AGND to AVDD) | -200 | 200 | nA | AGND to AVDD | 5 | ||
| VCM_REF | VCM_REF | 1.28 | 1.3 | 1.32 | V | Internal voltage; independent of supply | 5 |
| CM_OUT Output Voltage | VCM | 0.3 | 1.3 | 2.3 | V | No dc load | 5 |
| Respiration Input Voltage Range | 0.3 | 2.3 | V | AC-coupled, independent of supply | 5 | ||
| Respiration Input Bias Current | -10 | 1 | 10 | nA | EXT_RESP_xx pins over AGND to AVDD | 5 | |
| Respiration Frequency | 46.5 | 64 | kHz | Programmable frequency, see Table 30 | 5 | ||
| RLD Output Voltage Range | 0.2 | V | Upper limit printed as AVDD − 0.2 V | 6 | |||
| RLD_OUT Short-Circuit Current | -5 | 2 | 5 | mA | Output shorted to AVDD/AGND; external protection resistor required | 6 | |
| DC Lead-Off Current Accuracy | -10 | 10 | % | Of programmed value | 6 | ||
| AC Lead-Off Current Accuracy | -10 | 10 | % | Of programmed value, measured into low impedance | 6 | ||
| REFIN Input Range | 1.76 | 1.8 | 1.84 | V | Channel gain scales directly with REFIN | 6 | |
| REFIN Input Current | 450 | 675 | 950 | μA | Three ECG channels and respiration enabled | 6 | |
| REFOUT Output Voltage | VREF | 1.785 | 1.8 | 1.815 | V | 6 | |
| Calibration DAC Full-Scale Output Voltage | 2.64 | 2.7 | 2.76 | V | No load, nominal FS output is 1.5 × REFOUT | 6 | |
| Calibration DAC Zero-Scale Output Voltage | 0.24 | 0.3 | 0.36 | V | No load | 6 | |
| Calibration DAC DNL | DNL | -1 | 1 | LSB | 6 | ||
| Calibration DAC Test Tone Output Voltage | 0.9 | 1 | 1.1 | mV p-p | Rides on common-mode voltage, VCM_REF = 1.3 V | 6 | |
| Reference Tempco | -10 | 10 | ppm/°C | 6 | |||
| Input Offset Tempco | -2 | 2 | μV/°C | 4 | |||
| Digital I/O Supply Voltage | IOVDD | 1.65 | 3.6 | V | 4 | ||
| Operating Temperature | TA | -40 | 85 | °C | 4 | ||
| SCLK Cycle Time (IOVDD 3.3 V) | 25 | ns | IOVDD 3.3 V | 10 | |||
| SCLK Cycle Time (IOVDD 2.5 V) | 40 | ns | IOVDD 2.5 V | 10 | |||
| SCLK Cycle Time (IOVDD 1.8 V) | 50 | ns | IOVDD 1.8 V | 10 | |||
| SDO Delay tDO (IOVDD 3.3 V) | tDO | 8.5 | 11 | ns | SCLK falling edge to SDO valid; 15 pF; IOVDD 3.3 V | 10 | |
| SDO Delay tDO (IOVDD 2.5 V) | tDO | 11.5 | 19 | ns | SCLK falling edge to SDO valid; 15 pF; IOVDD 2.5 V | 10 | |
| SDO Delay tDO (IOVDD 1.8 V) | tDO | 20 | 24 | ns | SCLK falling edge to SDO valid; 15 pF; IOVDD 1.8 V | 10 | |
| CS Setup tCSSA (3.3 V) | tCSSA | 8.5 | ns | CS valid setup time to rising SCLK; IOVDD 3.3 V | 10 | ||
| SCLK High Time tCH | tCH | 8 | ns | SCLK high time | 10 | ||
| SCLK Low Time tCL | tCL | 8 | ns | SCLK low time | 10 | ||
| SDI Setup tDS | tDS | 2 | ns | SDI valid setup time from SCLK rising edge | 10 | ||
| SDI Hold tDH | tDH | 2 | ns | SDI valid hold time from SCLK rising edge | 10 | ||
| RESET Low Time | 20 | ns | Minimum pulse width; RESET is edge triggered | 10 | |||
| AVDD to AGND | AVDD | -0.3 | 6 | V | 13 | ||
| IOVDD to DGND | IOVDD | -0.3 | 6 | V | 13 | ||
| ADCVDD to AGND | ADCVDD | -0.3 | 2.5 | V | 13 | ||
| DVDD to DGND | DVDD | -0.3 | 2.5 | V | 13 | ||
| REFIN/REFOUT to REFGND | -0.3 | 2.1 | V | 13 | |||
| ECG Input Continuous Current | -10 | 10 | mA | 13 | |||
| Storage Temperature Range | -65 | 125 | °C | 13 | |||
| Operating Junction Temperature Range | -40 | 85 | °C | 13 | |||
| Junction Temperature | 150 | °C | max | 13 | |||
| ESD HBM | 2500 | V | 13 | ||||
| ESD FICDM | 1000 | V | 13 | ||||
| Thermal Resistance 64-Lead LQFP | θJA | 42.5 | °C/W | JEDEC 4-layer (2S2P) JESD51-7 board, natural convection | 13 |
CAD (KiCad official)
- Symbol:
ADAS1000-4BSTZ - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
adas1000-4bstz-etched.step/adas1000-4bstz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adas1000-4bstz.step/adas1000-4bstz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (73 pp, sha256
3c9d0da9331e07b1, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADAS1000-4BSTZ
**Analog Devices** · Pre-ordered Chips · LQFP-64(10x10)
ADAS1000-4BSTZ from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 18 | AVDD | power_in | Analog supply, to be decoupled per the Power Supply, Grounding, and Decoupling Strategy section. |
| 23 | AVDD | power_in | Analog supply, to be decoupled per the Power Supply, Grounding, and Decoupling Strategy section. |
| 58 | AVDD | power_in | Analog supply, to be decoupled per the Power Supply, Grounding, and Decoupling Strategy section. |
| 63 | AVDD | power_in | Analog supply, to be decoupled per the Power Supply, Grounding, and Decoupling Strategy section. |
| 35 | IOVDD | power_in | Digital supply for digital input/output voltage levels, with bypass capacitors as recommended in the datasheet. |
| 46 | IOVDD | power_in | Digital supply for digital input/output voltage levels, with bypass capacitors as recommended in the datasheet. |
| 26 | ADCVDD | power_in | Analog supply for the ADC from an on-chip regulator, mainly for decoupling; may be externally supplied at 1.8 V with VREG_EN tied to ground, and must not supply other functions. |
| 55 | ADCVDD | power_in | Analog supply for the ADC from an on-chip regulator, mainly for decoupling; may be externally supplied at 1.8 V with VREG_EN tied to ground, and must not supply other functions. |
| 30 | DVDD | power_in | Digital core supply from an on-chip regulator, mainly for decoupling; may be overdriven by an external 1.8 V supply with VREG_EN tied to ground. |
| 51 | DVDD | power_in | Digital core supply from an on-chip regulator, mainly for decoupling; may be overdriven by an external 1.8 V supply with VREG_EN tied to ground. |
| 2 | AGND | power_in | Analog ground. |
| 15 | AGND | power_in | Analog ground. |
| 24 | AGND | power_in | Analog ground. |
| 25 | AGND | power_in | Analog ground. |
| 56 | AGND | power_in | Analog ground. |
| 57 | AGND | power_in | Analog ground. |
| 31 | DGND | power_in | Digital ground. |
| 34 | DGND | power_in | Digital ground. |
| 40 | DGND | power_in | Digital ground. |
| 47 | DGND | power_in | Digital ground. |
| 50 | DGND | power_in | Digital ground. |
| 59 | VREG_EN | input | Enables or disables the internal ADCVDD and DVDD regulators; tie to AVDD to enable or to ground to disable. |
| 10 | ECG1_LA | input | Analog input, Left Arm (LA). |
| 11 | ECG2_LL | input | Analog input, Left Leg (LL). |
| 12 | ECG3_RA | input | Analog input, Right Arm (RA). |
| 4 | EXT_RESP_RA | input | Optional external respiration input. |
| 5 | EXT_RESP_LL | input | Optional external respiration input. |
| 6 | EXT_RESP_LA | input | Optional external respiration input. |
| 62 | RESPDAC_LL | output | Optional path for higher performance respiration resolution, respiration DAC drive, negative side 0. |
| 60 | SHIELD/RESPDAC_LA | output | User-configured shared pin: shield driver output (SHIELD) or respiration DAC drive negative side 1 (RESPDAC_LA). |
| 3 | RESPDAC_RA | output | Optional path for higher performance respiration resolution, respiration DAC drive, positive side. |
| 22 | CM_OUT/WCT | output | Common-mode output voltage (average of selected electrodes); not intended to drive current. |
| 19 | CM_IN | input | Common-mode input. |
| 21 | RLD_SJ | passive | Summing junction for the right leg drive amplifier. |
| 20 | RLD_OUT | output | Output and feedback junction for the right leg drive amplifier. |
| 61 | CAL_DAC_IO | bidirectional | Calibration DAC input/output: output for a primary device, input for a secondary device; not intended to drive current. |
| 9 | REFIN | input | Reference input; in standalone mode connect REFOUT to REFIN, with 10 μF (ESR < 0.2 Ω) in parallel with 0.1 μF bypass capacitors to GND close to the pin. |
| 8 | REFOUT | output | Reference output. |
| 7 | REFGND | power_in | Reference ground; connect to a clean ground. |
| 27 | XTAL1 | passive | External crystal connects between XTAL1 and XTAL2, each requiring a 15 pF capacitor to ground. |
| 28 | XTAL2 | passive | External crystal connects between XTAL1 and XTAL2, each requiring a 15 pF capacitor to ground. |
| 29 | CLK_IO | bidirectional | Buffered clock input/output: output for a primary device, input for a secondary device; powers up in high impedance. |
| 41 | CS | input | Chip select and frame sync, active low; can frame each word or the entire suite of data in framing mode. |
| 44 | SCLK | input | Serial clock input; data is clocked in on a rising edge and out on a falling edge. |
| 43 | SDI | input | Serial data input. |
| 53 | PD | input | Power-down, active low. |
| 45 | SDO | output | Serial data output for reading back register configuration data and for the data frames. |
| 42 | DRDY | output | Digital output indicating conversion data is ready when low and busy when high; the entire packet must be read for DRDY to return high. |
| 54 | RESET | input | Digital input with internal pull-up resistor that resets all internal nodes to their power-on reset values. |
| 52 | SYNC_GANG | bidirectional | Digital input/output for synchronization of ganged devices (output on primary, input on secondary); powers up in high impedance. |
| 36 | GPIO0/MCS | bidirectional | General-purpose I/O or primary 128 kHz SPI CS. |
| 37 | GPIO1/MSCLK | bidirectional | General-purpose I/O or primary 128 kHz SPI SCLK. |
| 38 | GPIO2/MSDO | bidirectional | General-purpose I/O or primary 128 kHz SPI SDO. |
| 39 | GPIO3 | bidirectional | General-purpose I/O. |
| 1 | NC | unconnected | No connect; do not connect to this pin. |
| 13 | NC | unconnected | No connect; do not connect to this pin. |
| 14 | NC | unconnected | No connect; do not connect to this pin. |
| 16 | NC | unconnected | No connect; do not connect to this pin. |
| 17 | NC | unconnected | No connect; do not connect to this pin. |
| 32 | NC | unconnected | No connect; do not connect to this pin. |
| 33 | NC | unconnected | No connect; do not connect to this pin. |
| 48 | NC | unconnected | No connect; do not connect to this pin. |
| 49 | NC | unconnected | No connect; do not connect to this pin. |
| 64 | NC | unconnected | No connect; do not connect to this pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LQFP-64(10x10) |
| Category | Interface ICs |
| Pins | 64 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Electrode Input Range GAIN 0 | | 0.3 | 1.3 | 2.3 | V | GAIN 0 (gain setting ×1.4) | 4 |
| Electrode Input Range GAIN 1 | | 0.63 | 1.3 | 1.97 | V | GAIN 1 (gain setting ×2.1) | 4 |
| Electrode Input Range GAIN 2 | | 0.8 | 1.3 | 1.8 | V | GAIN 2 (gain setting ×2.8) | 4 |
| Electrode Input Range GAIN 3 | | 0.97 | 1.3 | 1.63 | V | GAIN 3 (gain setting ×4.2) | 4 |
| Input Bias Current | | -40 | 1 | 40 | nA | Each electrode input; over operating range; dc and ac lead-off are disabled | 4 |
| Input Bias Current (AGND to AVDD) | | -200 | | 200 | nA | AGND to AVDD | 4 |
| CMRR | CMRR | 105 | 110 | | dB | 51 kΩ imbalance, 60 Hz with ±300 mV differential dc offset; with driven leg loop closed | 4 |
| Gain Error GAIN 0 to GAIN 2 | | -1 | 0.01 | 1 | % | GAIN 0 to GAIN 2, factory calibrated | 5 |
| Gain Error GAIN 3 | | -2 | 0.1 | 2 | % | GAIN 3 setting, no factory calibration | 5 |
| Gain Matching GAIN 0 to GAIN 2 | | -0.1 | 0.02 | 0.1 | % | GAIN 0 to GAIN 2 | 5 |
| Gain Matching GAIN 3 | | -0.5 | 0.1 | 0.5 | % | GAIN 3 | 5 |
| Gain Tempco | | | 25 | | ppm/°C | | 5 |
| Common-Mode Input Voltage Range | | 0.3 | | 2.3 | V | CM_IN pin | 5 |
| CM_IN Input Bias Current | | -40 | 1 | 40 | nA | Over operating range; dc and ac lead-off disabled | 5 |
| CM_IN Input Bias Current (AGND to AVDD) | | -200 | | 200 | nA | AGND to AVDD | 5 |
| VCM_REF | VCM_REF | 1.28 | 1.3 | 1.32 | V | Internal voltage; independent of supply | 5 |
| CM_OUT Output Voltage | VCM | 0.3 | 1.3 | 2.3 | V | No dc load | 5 |
| Respiration Input Voltage Range | | 0.3 | | 2.3 | V | AC-coupled, independent of supply | 5 |
| Respiration Input Bias Current | | -10 | 1 | 10 | nA | EXT_RESP_xx pins over AGND to AVDD | 5 |
| Respiration Frequency | | 46.5 | | 64 | kHz | Programmable frequency, see Table 30 | 5 |
| RLD Output Voltage Range | | 0.2 | | | V | Upper limit printed as AVDD − 0.2 V | 6 |
| RLD_OUT Short-Circuit Current | | -5 | 2 | 5 | mA | Output shorted to AVDD/AGND; external protection resistor required | 6 |
| DC Lead-Off Current Accuracy | | -10 | | 10 | % | Of programmed value | 6 |
| AC Lead-Off Current Accuracy | | -10 | | 10 | % | Of programmed value, measured into low impedance | 6 |
| REFIN Input Range | | 1.76 | 1.8 | 1.84 | V | Channel gain scales directly with REFIN | 6 |
| REFIN Input Current | | 450 | 675 | 950 | μA | Three ECG channels and respiration enabled | 6 |
| REFOUT Output Voltage | VREF | 1.785 | 1.8 | 1.815 | V | | 6 |
| Calibration DAC Full-Scale Output Voltage | | 2.64 | 2.7 | 2.76 | V | No load, nominal FS output is 1.5 × REFOUT | 6 |
| Calibration DAC Zero-Scale Output Voltage | | 0.24 | 0.3 | 0.36 | V | No load | 6 |
| Calibration DAC DNL | DNL | -1 | | 1 | LSB | | 6 |
| Calibration DAC Test Tone Output Voltage | | 0.9 | 1 | 1.1 | mV p-p | Rides on common-mode voltage, VCM_REF = 1.3 V | 6 |
| Reference Tempco | | -10 | | 10 | ppm/°C | | 6 |
| Input Offset Tempco | | -2 | | 2 | μV/°C | | 4 |
| Digital I/O Supply Voltage | IOVDD | 1.65 | | 3.6 | V | | 4 |
| Operating Temperature | TA | -40 | | 85 | °C | | 4 |
| SCLK Cycle Time (IOVDD 3.3 V) | | 25 | | | ns | IOVDD 3.3 V | 10 |
| SCLK Cycle Time (IOVDD 2.5 V) | | 40 | | | ns | IOVDD 2.5 V | 10 |
| SCLK Cycle Time (IOVDD 1.8 V) | | 50 | | | ns | IOVDD 1.8 V | 10 |
| SDO Delay tDO (IOVDD 3.3 V) | tDO | | 8.5 | 11 | ns | SCLK falling edge to SDO valid; 15 pF; IOVDD 3.3 V | 10 |
| SDO Delay tDO (IOVDD 2.5 V) | tDO | | 11.5 | 19 | ns | SCLK falling edge to SDO valid; 15 pF; IOVDD 2.5 V | 10 |
| SDO Delay tDO (IOVDD 1.8 V) | tDO | | 20 | 24 | ns | SCLK falling edge to SDO valid; 15 pF; IOVDD 1.8 V | 10 |
| CS Setup tCSSA (3.3 V) | tCSSA | 8.5 | | | ns | CS valid setup time to rising SCLK; IOVDD 3.3 V | 10 |
| SCLK High Time tCH | tCH | 8 | | | ns | SCLK high time | 10 |
| SCLK Low Time tCL | tCL | 8 | | | ns | SCLK low time | 10 |
| SDI Setup tDS | tDS | 2 | | | ns | SDI valid setup time from SCLK rising edge | 10 |
| SDI Hold tDH | tDH | 2 | | | ns | SDI valid hold time from SCLK rising edge | 10 |
| RESET Low Time | | 20 | | | ns | Minimum pulse width; RESET is edge triggered | 10 |
| AVDD to AGND | AVDD | -0.3 | | 6 | V | | 13 |
| IOVDD to DGND | IOVDD | -0.3 | | 6 | V | | 13 |
| ADCVDD to AGND | ADCVDD | -0.3 | | 2.5 | V | | 13 |
| DVDD to DGND | DVDD | -0.3 | | 2.5 | V | | 13 |
| REFIN/REFOUT to REFGND | | -0.3 | | 2.1 | V | | 13 |
| ECG Input Continuous Current | | -10 | | 10 | mA | | 13 |
| Storage Temperature Range | | -65 | | 125 | °C | | 13 |
| Operating Junction Temperature Range | | -40 | | 85 | °C | | 13 |
| Junction Temperature | | | | 150 | °C | max | 13 |
| ESD HBM | | | | 2500 | V | | 13 |
| ESD FICDM | | | | 1000 | V | | 13 |
| Thermal Resistance 64-Lead LQFP | θJA | | 42.5 | | °C/W | JEDEC 4-layer (2S2P) JESD51-7 board, natural convection | 13 |
## CAD (KiCad official)
- Symbol: `ADAS1000-4BSTZ`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `adas1000-4bstz-etched.step` / `adas1000-4bstz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adas1000-4bstz.step` / `adas1000-4bstz.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ADAS1000-3_1000-4.pdf) (73 pp, sha256 `3c9d0da9331e07b1`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/adas1000-4bstz-datasheet.pdf)