component
ADA4899-1YRDZ
Public Made by Adomby adom
Analog Devices Operational Amplifier, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADA4899-1YRDZ
Analog Devices · Operational Amplifier · SOIC-8-EP
ADA4899-1YRDZ from Analog Devices, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FEEDBACK | input | Dedicated feedback pin on the opposite side of the package, intended to connect the feedback network to the inverting input and isolate the output-pin capacitive load and package inductance from the feedback loop. |
| 2 | -IN | input | Inverting input; the internal antiparallel diodes limit the differential input voltage to approximately ±1.2 V, and the input common-mode range is −3.7 V to +3.7 V with ±5 V supplies. |
| 3 | +IN | input | Noninverting input; the input common-mode voltage range is −3.7 V to +3.7 V with ±5 V supplies and 1.3 V to 3.7 V with a +5 V supply. |
| 4 | -VS | power_in | Negative supply pin, one of two negative supply pins on the SOIC; the total supply range is 4.5 V to 12 V and the absolute maximum supply voltage is 12.6 V. |
| 5 | -VS | power_in | Second negative supply pin, provided so the SOIC supports both an input-isolated layout and a traditional SOIC board layout. |
| 6 | VOUT | output | Amplifier output; output swing is −3.7 V to +3.7 V with RL = 1 kΩ and −3.25 V to +3.25 V with RL = 100 Ω at ±5 V, with short-circuit current of 160/200 mA sinking/sourcing. |
| 7 | +VS | power_in | Positive supply pin; the operating range is 4.5 V to 12 V and the absolute maximum supply voltage is 12.6 V. |
| 8 | DISABLE | input | Three-state disable input: pulling it low (−5 V to +2.4 V at ±5 V supply) places the output in a high-impedance state, leaving it open enables normal operation, and pulling it within 0.7 V of +VS turns on the low input bias current mode. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8-EP |
| Category | Amplifiers/Comparators |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Range | 4.5 | 12 | V | 3 | |||
| Supply Voltage | 12.6 | V | 5 | ||||
| Differential Input Voltage | -1.2 | 1.2 | V | 5 | |||
| Differential Input Current | -10 | 10 | mA | 5 | |||
| Storage Temperature Range | -65 | 150 | °C | 5 | |||
| Operating Temperature Range | -40 | 125 | °C | 5 | |||
| Lead Temperature (Soldering 10 sec) | 300 | °C | Soldering 10 sec | 5 | |||
| Junction Temperature | 150 | °C | 5 | ||||
| Input Offset Voltage | 35 | 230 | µV | ±5 V supply | 3 | ||
| Input Bias Current | -6 | -12 | µA | ±5 V supply; DISABLE pin floating | 3 | ||
| Input Bias Current | -0.1 | -1 | µA | ±5 V supply; DISABLE pin = +VS | 3 | ||
| Input Bias Offset Current | 0.05 | 0.7 | µA | ±5 V supply | 3 | ||
| Open-Loop Gain | 82 | 85 | dB | ±5 V supply | 3 | ||
| Input Common-Mode Voltage Range | -3.7 | 3.7 | V | ±5 V supply | 3 | ||
| Common-Mode Rejection Ratio | 98 | 130 | dB | ±5 V supply | 3 | ||
| DISABLE Input Threshold Voltage | 2.4 | V | ±5 V supply; output disabled | 3 | |||
| Input Bias Current | 17 | 21 | µA | ±5 V supply; DISABLE = +VS (enabled) | 3 | ||
| Input Bias Current | -35 | -44 | µA | ±5 V supply; DISABLE = −VS (disabled) | 3 | ||
| Output Voltage Swing | -3.65 | 3.65 | V | ±5 V supply; RL = 1 kΩ | 3 | ||
| Output Voltage Swing | -3.13 | 3.15 | V | ±5 V supply; RL = 100 Ω | 3 | ||
| Quiescent Current | 14.7 | 16.2 | mA | ±5 V supply | 3 | ||
| Quiescent Current (Disabled) | 1.8 | 2.1 | mA | ±5 V supply; DISABLE = −VS | 3 | ||
| Positive Power Supply Rejection Ratio | 84 | 90 | dB | ±5 V supply; +VS = 4 V to 6 V (input referred) | 3 | ||
| Negative Power Supply Rejection Ratio | 87 | 93 | dB | ±5 V supply; −VS = −6 V to −4 V (input referred) | 3 | ||
| Input Offset Voltage | 5 | 210 | µV | +5 V supply | 4 | ||
| Input Bias Current | -6 | -12 | µA | +5 V supply; DISABLE pin floating | 4 | ||
| Input Bias Current | -0.2 | -1.5 | µA | +5 V supply; DISABLE pin = +VS | 4 | ||
| Open-Loop Gain | 76 | 80 | dB | +5 V supply | 4 | ||
| Input Common-Mode Voltage Range | 1.3 | 3.7 | V | +5 V supply | 4 | ||
| Common-Mode Rejection Ratio | 90 | 114 | dB | +5 V supply | 4 | ||
| DISABLE Input Threshold Voltage | 2.4 | V | +5 V supply; output disabled | 4 | |||
| Input Bias Current | 16 | 18 | µA | +5 V supply; DISABLE = +VS (enabled) | 4 | ||
| Input Bias Current | -33 | -42 | µA | +5 V supply; DISABLE = −VS (disabled) | 4 | ||
| Output Voltage Swing | 1.25 | 3.75 | V | +5 V supply; RL = 1 kΩ | 4 | ||
| Output Voltage Swing | 1.4 | 3.6 | V | +5 V supply; RL = 100 Ω | 4 | ||
| Quiescent Current | 14.3 | 16 | mA | +5 V supply | 4 | ||
| Quiescent Current (Disabled) | 1.5 | 1.7 | mA | +5 V supply; DISABLE = −VS | 4 | ||
| Positive Power Supply Rejection Ratio | 84 | 90 | dB | +5 V supply; +VS = 4.5 V to 5.5 V, −VS = 0 V (input referred) | 4 | ||
| Negative Power Supply Rejection Ratio | 86 | 90 | dB | +5 V supply; +VS = 5 V, −VS = −0.5 V to +0.5 V (input referred) | 4 | ||
| Thermal Resistance, Junction-to-Ambient | θJA | 70 | °C/W | EPAD 8-lead SOIC on JEDEC 4-layer board | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | ground and power planes under the pins of the ADA4899-1 should be cleared of copper to prevent the formation of parasitic | 16 |
CAD (KiCad official)
- Symbol:
ADA4899-1YRDZ - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
ada4899-1yrdz-etched.step/ada4899-1yrdz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ada4899-1yrdz.step/ada4899-1yrdz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (20 pp, sha256
d9af936c09dbf1f8, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADA4899-1YRDZ
**Analog Devices** · Operational Amplifier · SOIC-8-EP
ADA4899-1YRDZ from Analog Devices, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FEEDBACK | input | Dedicated feedback pin on the opposite side of the package, intended to connect the feedback network to the inverting input and isolate the output-pin capacitive load and package inductance from the feedback loop. |
| 2 | -IN | input | Inverting input; the internal antiparallel diodes limit the differential input voltage to approximately ±1.2 V, and the input common-mode range is −3.7 V to +3.7 V with ±5 V supplies. |
| 3 | +IN | input | Noninverting input; the input common-mode voltage range is −3.7 V to +3.7 V with ±5 V supplies and 1.3 V to 3.7 V with a +5 V supply. |
| 4 | -VS | power_in | Negative supply pin, one of two negative supply pins on the SOIC; the total supply range is 4.5 V to 12 V and the absolute maximum supply voltage is 12.6 V. |
| 5 | -VS | power_in | Second negative supply pin, provided so the SOIC supports both an input-isolated layout and a traditional SOIC board layout. |
| 6 | VOUT | output | Amplifier output; output swing is −3.7 V to +3.7 V with RL = 1 kΩ and −3.25 V to +3.25 V with RL = 100 Ω at ±5 V, with short-circuit current of 160/200 mA sinking/sourcing. |
| 7 | +VS | power_in | Positive supply pin; the operating range is 4.5 V to 12 V and the absolute maximum supply voltage is 12.6 V. |
| 8 | DISABLE | input | Three-state disable input: pulling it low (−5 V to +2.4 V at ±5 V supply) places the output in a high-impedance state, leaving it open enables normal operation, and pulling it within 0.7 V of +VS turns on the low input bias current mode. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8-EP |
| Category | Amplifiers/Comparators |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Range | | 4.5 | | 12 | V | | 3 |
| Supply Voltage | | | | 12.6 | V | | 5 |
| Differential Input Voltage | | -1.2 | | 1.2 | V | | 5 |
| Differential Input Current | | -10 | | 10 | mA | | 5 |
| Storage Temperature Range | | -65 | | 150 | °C | | 5 |
| Operating Temperature Range | | -40 | | 125 | °C | | 5 |
| Lead Temperature (Soldering 10 sec) | | | | 300 | °C | Soldering 10 sec | 5 |
| Junction Temperature | | | | 150 | °C | | 5 |
| Input Offset Voltage | | | 35 | 230 | µV | ±5 V supply | 3 |
| Input Bias Current | | | -6 | -12 | µA | ±5 V supply; DISABLE pin floating | 3 |
| Input Bias Current | | | -0.1 | -1 | µA | ±5 V supply; DISABLE pin = +VS | 3 |
| Input Bias Offset Current | | | 0.05 | 0.7 | µA | ±5 V supply | 3 |
| Open-Loop Gain | | 82 | 85 | | dB | ±5 V supply | 3 |
| Input Common-Mode Voltage Range | | -3.7 | | 3.7 | V | ±5 V supply | 3 |
| Common-Mode Rejection Ratio | | 98 | 130 | | dB | ±5 V supply | 3 |
| DISABLE Input Threshold Voltage | | | | 2.4 | V | ±5 V supply; output disabled | 3 |
| Input Bias Current | | | 17 | 21 | µA | ±5 V supply; DISABLE = +VS (enabled) | 3 |
| Input Bias Current | | | -35 | -44 | µA | ±5 V supply; DISABLE = −VS (disabled) | 3 |
| Output Voltage Swing | | -3.65 | | 3.65 | V | ±5 V supply; RL = 1 kΩ | 3 |
| Output Voltage Swing | | -3.13 | | 3.15 | V | ±5 V supply; RL = 100 Ω | 3 |
| Quiescent Current | | | 14.7 | 16.2 | mA | ±5 V supply | 3 |
| Quiescent Current (Disabled) | | | 1.8 | 2.1 | mA | ±5 V supply; DISABLE = −VS | 3 |
| Positive Power Supply Rejection Ratio | | 84 | 90 | | dB | ±5 V supply; +VS = 4 V to 6 V (input referred) | 3 |
| Negative Power Supply Rejection Ratio | | 87 | 93 | | dB | ±5 V supply; −VS = −6 V to −4 V (input referred) | 3 |
| Input Offset Voltage | | | 5 | 210 | µV | +5 V supply | 4 |
| Input Bias Current | | | -6 | -12 | µA | +5 V supply; DISABLE pin floating | 4 |
| Input Bias Current | | | -0.2 | -1.5 | µA | +5 V supply; DISABLE pin = +VS | 4 |
| Open-Loop Gain | | 76 | 80 | | dB | +5 V supply | 4 |
| Input Common-Mode Voltage Range | | 1.3 | | 3.7 | V | +5 V supply | 4 |
| Common-Mode Rejection Ratio | | 90 | 114 | | dB | +5 V supply | 4 |
| DISABLE Input Threshold Voltage | | | | 2.4 | V | +5 V supply; output disabled | 4 |
| Input Bias Current | | | 16 | 18 | µA | +5 V supply; DISABLE = +VS (enabled) | 4 |
| Input Bias Current | | | -33 | -42 | µA | +5 V supply; DISABLE = −VS (disabled) | 4 |
| Output Voltage Swing | | 1.25 | | 3.75 | V | +5 V supply; RL = 1 kΩ | 4 |
| Output Voltage Swing | | 1.4 | | 3.6 | V | +5 V supply; RL = 100 Ω | 4 |
| Quiescent Current | | | 14.3 | 16 | mA | +5 V supply | 4 |
| Quiescent Current (Disabled) | | | 1.5 | 1.7 | mA | +5 V supply; DISABLE = −VS | 4 |
| Positive Power Supply Rejection Ratio | | 84 | 90 | | dB | +5 V supply; +VS = 4.5 V to 5.5 V, −VS = 0 V (input referred) | 4 |
| Negative Power Supply Rejection Ratio | | 86 | 90 | | dB | +5 V supply; +VS = 5 V, −VS = −0.5 V to +0.5 V (input referred) | 4 |
| Thermal Resistance, Junction-to-Ambient | θJA | | 70 | | °C/W | EPAD 8-lead SOIC on JEDEC 4-layer board | 5 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | ground and power planes under the pins of the ADA4899-1 should be cleared of copper to prevent the formation of parasitic | 16 |
## CAD (KiCad official)
- Symbol: `ADA4899-1YRDZ`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files: `ada4899-1yrdz-etched.step` / `ada4899-1yrdz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ada4899-1yrdz.step` / `ada4899-1yrdz.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589041693572411392) (20 pp, sha256 `d9af936c09dbf1f8`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ada4899-1yrdz-datasheet.pdf)