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ADA4830-2WBCPZ-R7

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Analog Devices Differential Amplifiers, LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADA4830-2WBCPZ-R7

Analog Devices · Differential Amplifiers · LFCSP-16(3x3)

ADA4830-2WBCPZ-R7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INP1 input Positive input of channel 1; the inputs withstand direct short-to-battery voltages up to 18 V.
2 INN1 input Negative input of channel 1; the inputs withstand direct short-to-battery voltages up to 18 V.
3 INN2 input Negative input of channel 2; the inputs withstand direct short-to-battery voltages up to 18 V.
4 INP2 input Positive input of channel 2; the inputs withstand direct short-to-battery voltages up to 18 V.
5 VREF2 input Voltage reference input for channel 2 that sets the output dc bias; internally biased to +VS/2 when left floating, with an input range of 0.2 V to 3.9 V.
6 GND2 power_in Power supply ground for channel 2.
7 +VS2 power_in Positive power supply for channel 2; must be connected to the same voltage as +VS1 and bypassed with a 0.1 µF capacitor to ground. The supply range is 2.9 V to 5.5 V.
8 ENA2 input Enable input for channel 2; connect to +VS or float for normal operation and to ground to disable the channel.
9 VOUT2 output Amplifier output of channel 2.
10 STB2 output Short-to-battery indicator output for channel 2; open-drain, logic low indicates an overvoltage (short-to-battery) condition and requires an external pull-up resistor.
11 STB1 output Short-to-battery indicator output for channel 1; open-drain, logic low indicates an overvoltage (short-to-battery) condition and requires an external pull-up resistor.
12 VOUT1 output Amplifier output of channel 1.
13 ENA1 input Enable input for channel 1; connect to +VS or float for normal operation and to ground to disable the channel.
14 +VS1 power_in Positive power supply for channel 1; must be connected to the same voltage as +VS2 and bypassed with a 0.1 µF capacitor to ground. The supply range is 2.9 V to 5.5 V.
15 GND1 power_in Power supply ground for channel 1.
16 VREF1 input Voltage reference input for channel 1 that sets the output dc bias; internally biased to +VS/2 when left floating, with an input range of 0.2 V to 3.9 V.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-16(3x3)
Category Amplifiers/Comparators
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Nominal Gain (5 V operation) 0.49 0.5 0.51 V/V VIN to VOUT 3
Nominal Gain, automotive W (5 V operation) 0.49 0.51 V/V TMIN to TMAX 3
Output Bias Voltage (5 V operation) 2.45 2.5 2.55 V 3
Output Bias Voltage, automotive W (5 V operation) 2.44 2.56 V TMIN to TMAX 3
Input Common-Mode Voltage Range (5 V operation) -10 9.5 V VREF voltage adjusted to optimized range 3
Input Common-Mode Voltage Range, automotive W (5 V operation) -10 9.5 V TMIN to TMAX 3
Common-Mode Rejection (5 V operation) 42 65 dB VIN = ±5 V 3
Common-Mode Rejection, automotive W (5 V operation) 42 dB TMIN to TMAX 3
Protected Input Voltage Range (5 V operation) -9 20 V 3
Protected Input Voltage Range, automotive W (5 V operation) -9 20 V TMIN to TMAX 3
Short-to-Battery Output Flag Trigger Level (5 V operation) 9.8 10.3 10.8 V Minimum VIN needed to signal an input fault condition 3
Short-to-Battery Output Flag Trigger Level, automotive W (5 V operation) 9.8 10.8 V TMIN to TMAX 3
Voltage Reference Input Voltage Range 0.2 3.9 V 3
ENA Logic High Input Voltage VIH 3 V Voltage to enable device 3
ENA Logic Low Input Voltage VIL 1 V Voltage to disable device 3
Output Voltage Swing (5 V operation) 0.01 4.75 V RL = 150 Ω to ground 4
Quiescent Current per Amplifier (5 V operation) 6.8 10 mA Enabled (ENA = 5 V), no load 4
Quiescent Current per Amplifier, automotive W (5 V operation) 10.4 mA TMIN to TMAX 4
-3 dB Large Signal Bandwidth (5 V operation) 64 71 MHz VOUT = 0.5 V p-p, RL = 150 Ω 3
-3 dB Large Signal Bandwidth, automotive W (5 V operation) 56 MHz TMIN to TMAX 3
-3 dB Bandwidth (5 V operation) 65 74 MHz VOUT = 0.1 V p-p, RL = 150 Ω 3
-3 dB Bandwidth, automotive W (5 V operation) 60 MHz TMIN to TMAX 3
Nominal Gain (3.3 V operation) 0.49 0.5 0.51 V/V 3.3 V operation: VIN to VOUT 4
Output Bias Voltage (3.3 V operation) 1.6 1.65 1.7 V 3.3 V operation 4
Output Bias Voltage, automotive W (3.3 V operation) 1.59 1.71 V 3.3 V operation; TMIN to TMAX 4
Input Common-Mode Voltage Range (3.3 V operation) -8 6 V 3.3 V operation; VREF voltage adjusted to optimized range 4
Input Common-Mode Voltage Range, automotive W (3.3 V operation) -8 6 V 3.3 V operation; TMIN to TMAX 4
Common-Mode Rejection (3.3 V operation) 41 54 dB 3.3 V operation; VIN = ±3.3 V 4
Common-Mode Rejection, automotive W (3.3 V operation) 40 dB 3.3 V operation; TMIN to TMAX 4
Short-to-Battery Output Flag Trigger Level (3.3 V operation) 7.4 7.8 8.2 V 3.3 V operation; minimum VIN needed to signal an input fault condition 4
ENA Logic High Input Voltage (3.3 V operation) VIH 1.8 V 3.3 V operation; voltage to enable device 5
ENA Logic Low Input Voltage (3.3 V operation) VIL 0.8 V 3.3 V operation; voltage to disable device 5
Supply Voltage (+VS pin) +VS 6 V 6
Supply Voltage Delta, +VS1 to +VS2 (ADA4830-2 only) 0.5 V ADA4830-2 only 6
Input Voltage Positive Direction (INNx, INPx) 22 V 6
Input Voltage Negative Direction (INNx, INPx) -10 V 6
Storage Temperature Range -65 150 °C 6
Lead Temperature (Soldering) 260 °C Soldering, 10 sec 6
Junction Temperature 150 °C 6
Supply Voltage Operating Range +VS 2.9 5.5 V Operation outside of this range results in performance degradation 4
Operating Temperature Range -40 125 °C 4
Quiescent Current per Amplifier, disabled 90 µA Disabled (ENA = 0 V), no load 4
-3 dB Bandwidth (5 V operation) 84 MHz VOUT = 0.1 V p-p, RL = 1 kΩ 3
Bandwidth for 0.1 dB Flatness (5 V operation) 28 MHz VOUT = 0.5 V p-p, RL = 150 Ω 3
Settling Time to 0.1% (5 V operation) 25 ns VOUT = 2 V step 3
Output Voltage Noise 28 nV/√Hz f = 1 MHz 3
Differential Gain Error (NTSC) 0.1 % RL = 150 Ω, VIN = 1 V p-p 3
Differential Phase Error (NTSC) 0.1 degrees RL = 150 Ω, VIN = 1 V p-p 3
Signal-to-Noise Ratio 73 dB f = 100 kHz to 15 MHz, VOUT = 0.5 V p-p 3
Input Resistance (Differential Mode) 6.7 kΩ 3
Input Resistance (Common Mode) 2 kΩ 3
Input Current 4.1 mA VIN = 18 V (short-to-battery) 3
Voltage Reference Input Resistance 20 kΩ 3
STB Logic High Output Voltage VOH 5 V VIN ≤ 9.8 V (normal operation) 3
Power Supply Rejection Ratio (5 V operation) PSRR 53 dB +VS = 4.5 V to 5.5 V, VREF is forced to 2.5 V 4
Capacitive Load Drive 47 pF Peaking ≤ 3 dB 4
Thermal Resistance, junction-to-ambient (16-Lead LFCSP) θJA 54 °C/W EPAD soldered to 4-layer (2s2p) board, EIA/JESD 51-7 6
Thermal Resistance, junction-to-case (16-Lead LFCSP) θJC 6 °C/W 6

CAD (KiCad official)

  • Symbol: ADA4830-2WBCPZ-R7
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
  • 3D model files: ada4830-2wbcpz-r7-etched.step / ada4830-2wbcpz-r7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ada4830-2wbcpz-r7.step / ada4830-2wbcpz-r7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (22 pp, sha256 8b222ea78debcbef, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF