component
AD9959BCPZ-REEL7
Public Made by Adomby adom
Analog Devices Direct Digital Synthesis (DDS), LFCSP-56(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"schema_version": 1,
"type": "component",
"slug": "ad9959bcpz-reel7",
"title": "AD9959BCPZ-REEL7",
"brief": "Analog Devices Direct Digital Synthesis (DDS), LFCSP-56(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"data converters",
"ad9959bcpz-reel7",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "AD9959BCPZ-REEL7",
"manufacturer": "Analog Devices",
"package": "LFCSP-56(8x8)",
"pin_count": 57,
"category": "Data Converters",
"subcategory": "Direct Digital Synthesis (DDS)",
"datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9959.pdf",
"parts": {
"symbol": "ad9959bcpz-reel7.kicad_sym",
"footprint": "ad9959bcpz-reel7.kicad_mod",
"model_3d": "ad9959bcpz-reel7-hero.glb",
"model_3d_plain": "ad9959bcpz-reel7-etched.glb",
"model_3d_step": "ad9959bcpz-reel7-etched.step",
"model_3d_step_plain": "ad9959bcpz-reel7.step",
"lbr": "ad9959bcpz-reel7.lbr"
},
"distributor_links": {
"lcsc": "C653947",
"digikey": "AD9959BCPZ-REEL7TR-ND",
"mouser": "584-AD9959BCPZ-R7"
},
"distributor_check": {
"checked_at": "2026-10-31T03:48:42Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "AD9959BCPZ-REEL7TR-ND",
"status": "found"
},
"mouser": {
"pn": "584-AD9959BCPZ-R7",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "SYNC_IN",
"type": "input",
"description": "Used to synchronize multiple AD9959 devices; connects to the SYNC_OUT pin of the master AD9959 device."
},
{
"number": "2",
"name": "SYNC_OUT",
"type": "output",
"description": "Used to synchronize multiple AD9959 devices; connects to the SYNC_IN pin of the slave AD9959 devices."
},
{
"number": "3",
"name": "MASTER_RESET",
"type": "input",
"description": "Active-high reset pin that forces the internal registers to their default state when asserted."
},
{
"number": "4",
"name": "PWR_DWN_CTL",
"type": "input",
"description": "External power-down control; when high, the device enters the power-down mode selected by FR1[6]."
},
{
"number": "5",
"name": "AVDD",
"type": "power_in",
"description": "Analog power supply pin, 1.8 V."
},
{
"number": "6",
"name": "AGND",
"type": "power_in",
"description": "Analog ground pin."
},
{
"number": "7",
"name": "AVDD",
"type": "power_in",
"description": "Analog power supply pin, 1.8 V."
},
{
"number": "8",
"name": "CH2_IOUT",
"type": "output",
"description": "True DAC output for Channel 2; terminates into AVDD."
},
{
"number": "9",
"name": "CH2_IOUT",
"type": "output",
"description": "Complementary DAC output for Channel 2; terminates into AVDD."
},
{
"number": "10",
"name": "AGND",
"type": "power_in",
"description": "Analog ground pin."
},
{
"number": "11",
"name": "AVDD",
"type": "power_in",
"description": "Analog power supply pin, 1.8 V."
},
{
"number": "12",
"name": "AGND",
"type": "power_in",
"description": "Analog ground pin."
},
{
"number": "13",
"name": "CH3_IOUT",
"type": "output",
"description": "True DAC output for Channel 3; terminates into AVDD."
},
{
"number": "14",
"name": "CH3_IOUT",
"type": "output",
"description": "Complementary DAC output for Channel 3; terminates into AVDD."
},
{
"number": "15",
"name": "AVDD",
"type": "power_in",
"description": "Analog power supply pin, 1.8 V."
},
{
"number": "16",
"name": "AGND",
"type": "power_in",
"description": "Analog ground pin."
},
{
"number": "17",
"name": "DAC_RSET",
"type": "input",
"description": "Establishes the reference current for all DACs; a 1.91 kΩ (nominal) resistor is connected from this pin to AGND."
},
{
"number": "18",
"name": "AGND",
"type": "power_in",
"description": "Analog ground pin."
},
{
"number": "19",
"name": "AVDD",
"type": "power_in",
"description": "Analog power supply pin, 1.8 V."
},
{
"number": "20",
"name": "AGND",
"type": "power_in",
"description": "Analog ground pin."
},
{
"number": "21",
"name": "AVDD",
"type": "power_in",
"description": "Analog power supply pin, 1.8 V."
},
{
"number": "22",
"name": "REF_CLK",
"type": "input",
"description": "Complementary reference clock/oscillator input; when used in single-ended mode, decouple this pin to AVDD or AGND with a 0.1 µF capacitor."
},
{
"number": "23",
"name": "REF_CLK",
"type": "input",
"description": "Reference clock/oscillator input; this is the input when the REF_CLK is operated in single-ended mode."
},
{
"number": "24",
"name": "CLK_MODE_SEL",
"type": "input",
"description": "Controls the oscillator section: high (1.8 V) enables crystal operation, low bypasses it; do not drive this pin beyond 1.8 V."
},
{
"number": "25",
"name": "AGND",
"type": "power_in",
"description": "Analog ground pin."
},
{
"number": "26",
"name": "AVDD",
"type": "power_in",
"description": "Analog power supply pin, 1.8 V."
},
{
"number": "27",
"name": "LOOP_FILTER",
"type": "input",
"description": "Connects to the external zero compensation network of the PLL loop filter, typically 0 Ω in series with 680 pF tied to AVDD."
},
{
"number": "28",
"name": "AGND",
"type": "power_in",
"description": "Analog ground pin."
},
{
"number": "29",
"name": "CH0_IOUT",
"type": "output",
"description": "Complementary DAC output for Channel 0; terminates into AVDD."
},
{
"number": "30",
"name": "CH0_IOUT",
"type": "output",
"description": "True DAC output for Channel 0; terminates into AVDD."
},
{
"number": "31",
"name": "AVDD",
"type": "power_in",
"description": "Analog power supply pin, 1.8 V."
},
{
"number": "32",
"name": "AGND",
"type": "power_in",
"description": "Analog ground pin."
},
{
"number": "33",
"name": "AVDD",
"type": "power_in",
"description": "Analog power supply pin, 1.8 V."
},
{
"number": "34",
"name": "AGND",
"type": "power_in",
"description": "Analog ground pin."
},
{
"number": "35",
"name": "CH1_IOUT",
"type": "output",
"description": "Complementary DAC output for Channel 1; terminates into AVDD."
},
{
"number": "36",
"name": "CH1_IOUT",
"type": "output",
"description": "True DAC output for Channel 1; terminates into AVDD."
},
{
"number": "37",
"name": "AVDD",
"type": "power_in",
"description": "Analog power supply pin, 1.8 V."
},
{
"number": "38",
"name": "AGND",
"type": "power_in",
"description": "Analog ground pin."
},
{
"number": "39",
"name": "AVDD",
"type": "power_in",
"description": "Analog power supply pin, 1.8 V."
},
{
"number": "40",
"name": "P0",
"type": "input",
"description": "Profile data pin for modulation, sweep start/stop, or RU/RD; data is synchronous to SYNC_CLK and must meet its setup and hold times."
},
{
"number": "41",
"name": "P1",
"type": "input",
"description": "Profile data pin for modulation, sweep start/stop, or RU/RD; data is synchronous to SYNC_CLK and must meet its setup and hold times."
},
{
"number": "42",
"name": "P2",
"type": "input",
"description": "Profile data pin for modulation, sweep start/stop, or RU/RD; data is synchronous to SYNC_CLK and must meet its setup and hold times."
},
{
"number": "43",
"name": "P3",
"type": "input",
"description": "Profile data pin for modulation, sweep start/stop, or RU/RD; data is synchronous to SYNC_CLK and must meet its setup and hold times."
},
{
"number": "44",
"name": "DGND",
"type": "power_in",
"description": "Digital power ground pin."
},
{
"number": "45",
"name": "DVDD",
"type": "power_in",
"description": "Digital power supply pin, 1.8 V."
},
{
"number": "46",
"name": "I/O_UPDATE",
"type": "input",
"description": "A rising edge transfers data from the serial I/O buffer to active registers; it is synchronous to SYNC_CLK with a minimum pulse width of one SYNC_CLK period."
},
{
"number": "47",
"name": "CS",
"type": "input",
"description": "Active-low chip select that allows multiple devices to share a common SPI bus."
},
{
"number": "48",
"name": "SCLK",
"type": "input",
"description": "Serial data clock; data is written on the rising edge and read on the falling edge, with a maximum SCLK toggle frequency of 200 MHz."
},
{
"number": "49",
"name": "DVDD_I/O",
"type": "power_in",
"description": "3.3 V digital power supply for the SPI port and digital I/O; must be connected to 3.3 V."
},
{
"number": "50",
"name": "SDIO_0",
"type": "bidirectional",
"description": "Dedicated serial port data I/O pin."
},
{
"number": "51",
"name": "SDIO_1",
"type": "bidirectional",
"description": "Serial data I/O pin that can alternatively be used to initiate ramp-up/ramp-down (RU/RD) of the DAC output amplitude."
},
{
"number": "52",
"name": "SDIO_2",
"type": "bidirectional",
"description": "Serial data I/O pin that can alternatively be used to initiate ramp-up/ramp-down (RU/RD) of the DAC output amplitude."
},
{
"number": "53",
"name": "SDIO_3",
"type": "bidirectional",
"description": "Serial data I/O pin that can also initiate RU/RD and serves as SYNC_I/O in 1-bit and 2-bit modes; do not let it float in those modes."
},
{
"number": "54",
"name": "SYNC_CLK",
"type": "output",
"description": "Runs at one-fourth the system clock rate and can be disabled; I/O_UPDATE and profile data are synchronous to it."
},
{
"number": "55",
"name": "DVDD",
"type": "power_in",
"description": "Digital power supply pin, 1.8 V."
},
{
"number": "56",
"name": "DGND",
"type": "power_in",
"description": "Digital power ground pin."
},
{
"number": "57",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The overbar marking the complementary (inverted) outputs and the complementary REF_CLK input is lost; Table 3 classifies DAC_RSET and LOOP_FILTER as digital inputs (I), but they are a resistor and an RC; The 56-lead LFCSP has an exposed pad on the bottom side that is not a numbered pin; the datasheet re",
"exposed pad 57 added from the footprint"
],
"pages_sent": 27,
"cost_usd": 0.2085,
"at": "2026-10-31T03:48:25"
},
"datasheet": {
"url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9959.pdf",
"pages": 44,
"sha256": "0b6966ac048d7b55",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 57,
"described": 57,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "ad9959bcpz-reel7.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
8,
8,
1
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "54eb482f12c9d8b70c1bfc78306a1c34f412f3556e225cbd097840e5abdb7981",
"checked": "2026-10-31",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ad9959bcpz-reel7-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
8,
8,
1
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "7607870db788f0230ae853f73948292b81b498a827065dbbd9f3711358bd77d2",
"checked": "2026-10-31",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
],
"package_dims": {
"package_code": "CP-56-1",
"source_page": 44,
"D": {
"nom_mm": 8,
"range_mm": [
7.9,
8.1
]
},
"E1": {
"nom_mm": 8,
"range_mm": [
7.9,
8.1
]
},
"e": {
"nom_mm": 0.5,
"range_mm": [
null,
null
]
},
"A": {
"nom_mm": 0.85,
"range_mm": [
0.8,
1
]
},
"source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
"model_check": {
"file": "ad9959bcpz-reel7.step",
"verdict": "PASS",
"reasons": [
"height within the datasheet's package drawing"
],
"by": "factory/package_fit.py"
}
}
},
"metadata": {
"specs": {
"Manufacturer": "Analog Devices",
"Package": "LFCSP-56(8x8)",
"Category": "Data Converters",
"Pins": "57"
},
"characteristics": {
"version": 1,
"source": "datasheet",
"datasheet_sha256": "0b6966ac048d7b5564bd1b4c7f0e7fa052b3d9168fae5008a29829c8409e46dc",
"rows": [
{
"name": "Reference clock input frequency, REFCLK multiplier bypassed",
"symbol": "",
"kind": "electrical",
"unit": "MHz",
"min": 1,
"typ": null,
"max": 500,
"conditions": "REFCLK Multiplier Bypassed",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Reference clock input frequency, REFCLK multiplier enabled",
"symbol": "",
"kind": "electrical",
"unit": "MHz",
"min": 10,
"typ": null,
"max": 125,
"conditions": "REFCLK Multiplier Enabled",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Internal VCO output frequency range, VCO gain control bit high",
"symbol": "",
"kind": "electrical",
"unit": "MHz",
"min": 255,
"typ": null,
"max": 500,
"conditions": "VCO Gain Control Bit Set High",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Internal VCO output frequency range, VCO gain control bit low",
"symbol": "",
"kind": "electrical",
"unit": "MHz",
"min": 100,
"typ": null,
"max": 160,
"conditions": "VCO Gain Control Bit Set Low",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Crystal REFCLK source frequency range",
"symbol": "",
"kind": "electrical",
"unit": "MHz",
"min": 20,
"typ": null,
"max": 30,
"conditions": "",
"source_page": 4,
"source": "datasheet"
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{
"name": "Reference clock input level",
"symbol": "",
"kind": "electrical",
"unit": "mV",
"min": 200,
"typ": null,
"max": 1000,
"conditions": "Measured at each pin (single-ended)",
"source_page": 4,
"source": "datasheet"
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{
"name": "Duty cycle with REFCLK multiplier bypassed",
"symbol": "",
"kind": "electrical",
"unit": "%",
"min": 45,
"typ": null,
"max": 55,
"conditions": "REFCLK Multiplier Bypassed",
"source_page": 4,
"source": "datasheet"
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{
"name": "Duty cycle with REFCLK multiplier enabled",
"symbol": "",
"kind": "electrical",
"unit": "%",
"min": 35,
"typ": null,
"max": 65,
"conditions": "REFCLK Multiplier Enabled",
"source_page": 4,
"source": "datasheet"
},
{
"name": "CLK_MODE_SEL (Pin 24) logic 1 voltage",
"symbol": "",
"kind": "electrical",
"unit": "V",
"min": 1.25,
"typ": 1.8,
"max": null,
"conditions": "1.8 V digital input logic",
"source_page": 4,
"source": "datasheet"
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{
"name": "CLK_MODE_SEL (Pin 24) logic 0 voltage",
"symbol": "",
"kind": "electrical",
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"min": null,
"typ": null,
"max": 0.5,
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"source_page": 4,
"source": "datasheet"
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{
"name": "DAC full-scale output current",
"symbol": "",
"kind": "electrical",
"unit": "mA",
"min": 1.25,
"typ": null,
"max": 10,
"conditions": "",
"source_page": 4,
"source": "datasheet"
},
{
"name": "DAC gain error",
"symbol": "",
"kind": "tolerance",
"unit": "%FS",
"min": -10,
"typ": null,
"max": 10,
"conditions": "",
"source_page": 4,
"source": "datasheet"
},
{
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