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AD9959BCPZ-REEL7

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Analog Devices Direct Digital Synthesis (DDS), LFCSP-56(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Verified AD9959BCPZ-REEL7

by Ray · last 31 Oct 2026 · 1 record · files match
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Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 57 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD9959BCPZ-REEL7 · LFCSP-56(8x8) · 57 pins
  • ✓copper: 57 copper pads, none touching another net
  • ✓datasheet: all 57 pin names found in the 44-page datasheet
  • ✓distributor: lcsc C653947, digikey AD9959BCPZ-REEL7TR-ND, mouser 584-AD9959BCPZ-R7
  • ✓family: QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-nb9f213_/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.44)
  • ✓pads: 57 pins = 57 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 57 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad9959bcpz-reel7.kicad_sym✓ ad9959bcpz-reel7.kicad_mod✓ ad9959bcpz-reel7.step
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Ray Publish 0.1.0 c6fdb4d 3d ago

AD9959BCPZ-REEL7

Analog Devices · Direct Digital Synthesis (DDS) · LFCSP-56(8x8)

AD9959BCPZ-REEL7 from Analog Devices, in a LFCSP-56(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SYNC_IN input Used to synchronize multiple AD9959 devices; connects to the SYNC_OUT pin of the master AD9959 device.
2 SYNC_OUT output Used to synchronize multiple AD9959 devices; connects to the SYNC_IN pin of the slave AD9959 devices.
3 MASTER_RESET input Active-high reset pin that forces the internal registers to their default state when asserted.
4 PWR_DWN_CTL input External power-down control; when high, the device enters the power-down mode selected by FR1[6].
5 AVDD power_in Analog power supply pin, 1.8 V.
6 AGND power_in Analog ground pin.
7 AVDD power_in Analog power supply pin, 1.8 V.
8 CH2_IOUT output True DAC output for Channel 2; terminates into AVDD.
9 CH2_IOUT output Complementary DAC output for Channel 2; terminates into AVDD.
10 AGND power_in Analog ground pin.
11 AVDD power_in Analog power supply pin, 1.8 V.
12 AGND power_in Analog ground pin.
13 CH3_IOUT output True DAC output for Channel 3; terminates into AVDD.
14 CH3_IOUT output Complementary DAC output for Channel 3; terminates into AVDD.
15 AVDD power_in Analog power supply pin, 1.8 V.
16 AGND power_in Analog ground pin.
17 DAC_RSET input Establishes the reference current for all DACs; a 1.91 kΩ (nominal) resistor is connected from this pin to AGND.
18 AGND power_in Analog ground pin.
19 AVDD power_in Analog power supply pin, 1.8 V.
20 AGND power_in Analog ground pin.
21 AVDD power_in Analog power supply pin, 1.8 V.
22 REF_CLK input Complementary reference clock/oscillator input; when used in single-ended mode, decouple this pin to AVDD or AGND with a 0.1 µF capacitor.
23 REF_CLK input Reference clock/oscillator input; this is the input when the REF_CLK is operated in single-ended mode.
24 CLK_MODE_SEL input Controls the oscillator section: high (1.8 V) enables crystal operation, low bypasses it; do not drive this pin beyond 1.8 V.
25 AGND power_in Analog ground pin.
26 AVDD power_in Analog power supply pin, 1.8 V.
27 LOOP_FILTER input Connects to the external zero compensation network of the PLL loop filter, typically 0 Ω in series with 680 pF tied to AVDD.
28 AGND power_in Analog ground pin.
29 CH0_IOUT output Complementary DAC output for Channel 0; terminates into AVDD.
30 CH0_IOUT output True DAC output for Channel 0; terminates into AVDD.
31 AVDD power_in Analog power supply pin, 1.8 V.
32 AGND power_in Analog ground pin.
33 AVDD power_in Analog power supply pin, 1.8 V.
34 AGND power_in Analog ground pin.
35 CH1_IOUT output Complementary DAC output for Channel 1; terminates into AVDD.
36 CH1_IOUT output True DAC output for Channel 1; terminates into AVDD.
37 AVDD power_in Analog power supply pin, 1.8 V.
38 AGND power_in Analog ground pin.
39 AVDD power_in Analog power supply pin, 1.8 V.
40 P0 input Profile data pin for modulation, sweep start/stop, or RU/RD; data is synchronous to SYNC_CLK and must meet its setup and hold times.
41 P1 input Profile data pin for modulation, sweep start/stop, or RU/RD; data is synchronous to SYNC_CLK and must meet its setup and hold times.
42 P2 input Profile data pin for modulation, sweep start/stop, or RU/RD; data is synchronous to SYNC_CLK and must meet its setup and hold times.
43 P3 input Profile data pin for modulation, sweep start/stop, or RU/RD; data is synchronous to SYNC_CLK and must meet its setup and hold times.
44 DGND power_in Digital power ground pin.
45 DVDD power_in Digital power supply pin, 1.8 V.
46 I/O_UPDATE input A rising edge transfers data from the serial I/O buffer to active registers; it is synchronous to SYNC_CLK with a minimum pulse width of one SYNC_CLK period.
47 CS input Active-low chip select that allows multiple devices to share a common SPI bus.
48 SCLK input Serial data clock; data is written on the rising edge and read on the falling edge, with a maximum SCLK toggle frequency of 200 MHz.
49 DVDD_I/O power_in 3.3 V digital power supply for the SPI port and digital I/O; must be connected to 3.3 V.
50 SDIO_0 bidirectional Dedicated serial port data I/O pin.
51 SDIO_1 bidirectional Serial data I/O pin that can alternatively be used to initiate ramp-up/ramp-down (RU/RD) of the DAC output amplitude.
52 SDIO_2 bidirectional Serial data I/O pin that can alternatively be used to initiate ramp-up/ramp-down (RU/RD) of the DAC output amplitude.
53 SDIO_3 bidirectional Serial data I/O pin that can also initiate RU/RD and serves as SYNC_I/O in 1-bit and 2-bit modes; do not let it float in those modes.
54 SYNC_CLK output Runs at one-fourth the system clock rate and can be disabled; I/O_UPDATE and profile data are synchronous to it.
55 DVDD power_in Digital power supply pin, 1.8 V.
56 DGND power_in Digital power ground pin.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-56(8x8)
Category Data Converters
Pins 57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Reference clock input frequency, REFCLK multiplier bypassed 1 500 MHz REFCLK Multiplier Bypassed 4
Reference clock input frequency, REFCLK multiplier enabled 10 125 MHz REFCLK Multiplier Enabled 4
Internal VCO output frequency range, VCO gain control bit high 255 500 MHz VCO Gain Control Bit Set High 4
Internal VCO output frequency range, VCO gain control bit low 100 160 MHz VCO Gain Control Bit Set Low 4
Crystal REFCLK source frequency range 20 30 MHz 4
Reference clock input level 200 1000 mV Measured at each pin (single-ended) 4
Duty cycle with REFCLK multiplier bypassed 45 55 % REFCLK Multiplier Bypassed 4
Duty cycle with REFCLK multiplier enabled 35 65 % REFCLK Multiplier Enabled 4
CLK_MODE_SEL (Pin 24) logic 1 voltage 1.25 1.8 V 1.8 V digital input logic 4
CLK_MODE_SEL (Pin 24) logic 0 voltage 0.5 V 1.8 V digital input logic 4
DAC full-scale output current 1.25 10 mA 4
DAC gain error -10 10 %FS 4
Channel-to-channel output amplitude matching error -2.5 2.5 % 4
DAC output current offset 1 25 µA 4
DAC differential nonlinearity -0.5 0.5 LSB 4
DAC integral nonlinearity -1 1 LSB 4
Channel-to-channel isolation 65 dB DAC supplies tied together (see Figure 19) 4
Maximum serial clock (SCLK) frequency 200 MHz 6
Minimum SCLK pulse width low tPWL 1.6 ns 6
Minimum SCLK pulse width high tPWH 2.2 ns 6
Minimum data setup time tDS 2.2 ns 6
Minimum data hold time 0 ns 6
Minimum CS setup time tPRE 1 ns 6
Minimum data valid time for read operation 12 ns 6
MASTER_RESET minimum pulse width 1 SYNC_CLK period Min pulse width = 1 sync clock period 6
I/O_UPDATE minimum pulse width 1 SYNC_CLK period Min pulse width = 1 sync clock period 6
Minimum setup time, I/O_UPDATE to SYNC_CLK 4.8 ns Rising edge to rising edge 6
Minimum hold time, I/O_UPDATE to SYNC_CLK 0 ns Rising edge to rising edge 6
Minimum setup time, profile inputs to SYNC_CLK 5.4 ns 6
Minimum hold time, profile inputs to SYNC_CLK 0 ns 6
Minimum setup time, SDIO inputs to SYNC_CLK 2.5 ns 6
Minimum hold time, SDIO inputs to SYNC_CLK 0 ns 6
Propagation time between REF_CLK and SYNC_CLK 2.25 3.5 5.5 ns 6
CMOS logic input high voltage VIH 2 V 6
CMOS logic input low voltage VIL 0.8 V 6
CMOS logic 1 input current 3 12 µA 6
CMOS logic 0 input current -12 µA 6
CMOS logic output high voltage VOH 2.7 V 1 mA load 7
CMOS logic output low voltage VOL 0.4 V 1 mA load 7
IAVDD supply current, all channels on, single-tone mode IAVDD 155 180 mA All channels on, single-tone mode 7
IAVDD supply current, all channels on, sweep accumulator, REFCLK multiplier and 10-bit output scalar enabled IAVDD 160 185 mA All channels on, sweep accumulator, REFCLK multiplier and 10-bit output scalar enabled 7
IDVDD supply current, all channels on, single-tone mode IDVDD 105 125 mA All channels on, single-tone mode 7
IDVDD supply current, all channels on, sweep accumulator, REFCLK multiplier and 10-bit output scalar enabled IDVDD 125 145 mA All channels on, sweep accumulator, REFCLK multiplier and 10-bit output scalar enabled 7
IAVDD power-down mode current IAVDD 0.7 mA Power-down mode 7
IDVDD power-down mode current IDVDD 1.1 mA Power-down mode 7
DVDD_I/O (pin 49) supply voltage, absolute maximum DVDD_I/O 4 V 8
AVDD and DVDD supply voltage, absolute maximum AVDD, DVDD 2 V 8
Digital input voltage, absolute maximum -0.7 4 V DVDD_I/O = 3.3 V 8
Digital output current, absolute maximum 5 mA 8
Storage temperature range -65 150 °C 8
Operating temperature range -40 85 °C 8
Lead temperature 300 °C 10 sec soldering 8
Maximum junction temperature 150 °C 8
AVDD and DVDD supply tolerance AVDD, DVDD -5 5 % AVDD and DVDD = 1.8 V ± 5% 4
DVDD_I/O supply tolerance DVDD_I/O -5 5 % DVDD_I/O = 3.3 V ± 5% 4
Junction-to-ambient thermal resistance θJA 21 °C/W 8
Junction-to-case thermal resistance θJC 2 °C/W 8
AVDD and DVDD supply voltage, nominal AVDD, DVDD 1.8 V AVDD and DVDD = 1.8 V ± 5%; T = 25°C 4
DAC reference resistor RSET, nominal RSET 1.91 kΩ Connected from DAC_RSET (pin 17) to AGND 9
PLL loop filter zero-compensation capacitor, typical 680 pF Typical network with 0 Ω series resistor, tied to AVDD 10

CAD (KiCad official)

  • Symbol: AD9959BCPZ-REEL7
  • Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • 3D model: LFCSP-56(8x8) (KiCad packages3D, STEP)
  • 3D model files: ad9959bcpz-reel7-etched.step / ad9959bcpz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9959bcpz-reel7.step / ad9959bcpz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (44 pp, sha256 0b6966ac048d7b55, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF