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AD9957BSVZ

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Analog Devices Digital To Analog Converters (DACs), TQFP-100-EP(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD9957BSVZ

Analog Devices · Digital To Analog Converters (DACs) · TQFP-100-EP(14x14)

AD9957BSVZ from Analog Devices, in a TQFP-100-EP(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Not connected; allow the pin to float.
2 PLL_LOOP_FILTER input PLL loop filter compensation pin for the external loop filter components.
3 AVDD (1.8V) power_in 1.8 V analog core supply for the REFCLK PLL, nominally 1.8 V ±5%.
4 AGND power_in Analog ground.
5 AGND power_in Analog ground.
6 AVDD (1.8V) power_in 1.8 V analog core supply, nominally 1.8 V ±5%.
7 SYNC_IN+ input Synchronization digital input, rising-edge active, from an external master.
8 SYNC_IN− input Synchronization digital input, falling-edge active, from an external master.
9 SYNC_OUT+ output Synchronization digital output, rising-edge active, to external slave devices.
10 SYNC_OUT− output Synchronization digital output, falling-edge active, to external slave devices.
11 DVDD_I/O (3.3V) power_in 3.3 V digital input/output supply, nominally 3.3 V ±5%.
12 SYNC_SMP_ERR output Active-high output that goes high when no valid sync signal is received on SYNC_IN+/SYNC_IN-.
13 DGND power_in Digital ground.
14 MASTER_RESET input Active-high digital input that clears all memory elements and sets registers to default values.
15 DVDD_I/O (3.3V) power_in 3.3 V digital input/output supply, nominally 3.3 V ±5%.
16 DGND power_in Digital ground.
17 DVDD (1.8V) power_in 1.8 V digital core supply, nominally 1.8 V ±5%.
18 EXT_PWR_DWN input Active-high external power-down input that starts the programmed power-down mode; tie to ground if unused.
19 PLL_LOCK output Active-high output that indicates the clock multiplier PLL has locked to the reference clock.
20 CCI_OVFL output Active-high output that indicates a CCI filter overflow and stays high until the condition is cleared.
21 DVDD_I/O (3.3V) power_in 3.3 V digital input/output supply, nominally 3.3 V ±5%.
22 DGND power_in Digital ground.
23 DVDD (1.8V) power_in 1.8 V digital core supply, nominally 1.8 V ±5%.
24 NC unconnected Not connected; allow the pin to float.
25 D17 bidirectional Parallel data input bus bit 17 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
26 D16 bidirectional Parallel data input bus bit 16 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
27 D15 bidirectional Parallel data input bus bit 15 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
28 DVDD_I/O (3.3V) power_in 3.3 V digital input/output supply, nominally 3.3 V ±5%.
29 DGND power_in Digital ground.
30 DVDD (1.8V) power_in 1.8 V digital core supply, nominally 1.8 V ±5%.
31 D14 bidirectional Parallel data input bus bit 14 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
32 D13 bidirectional Parallel data input bus bit 13 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
33 D12 bidirectional Parallel data input bus bit 12 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
34 D11 bidirectional Parallel data input bus bit 11 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
35 D10 bidirectional Parallel data input bus bit 10 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
36 D9 bidirectional Parallel data input bus bit 9 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
37 D8 bidirectional Parallel data input bus bit 8 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
38 D7 bidirectional Parallel data input bus bit 7 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
39 D6 bidirectional Parallel data input bus bit 6 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
40 PDCLK output Parallel data clock output running at the sample rate of the parallel data port; logic 0 when disabled.
41 TxENABLE/FS input Active-high transmit enable input that gates the parallel data; in Blackfin interface mode it is the FS input.
42 D5/SPORT I-DATA bidirectional Parallel data bit 5 (active high); in Blackfin interface mode it is the serial I-data input.
43 D4/SPORT Q-DATA bidirectional Parallel data bit 4 (active high); in Blackfin interface mode it is the serial Q-data input.
44 D3 bidirectional Parallel data input bus bit 3 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
45 DVDD_I/O (3.3V) power_in 3.3 V digital input/output supply, nominally 3.3 V ±5%.
46 DGND power_in Digital ground.
47 DVDD (1.8V) power_in 1.8 V digital core supply, nominally 1.8 V ±5%.
48 D2 bidirectional Parallel data input bus bit 2 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
49 D1 bidirectional Parallel data input bus bit 1 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
50 D0 bidirectional Parallel data input bus bit 0 (active high), carrying the 18-bit I/Q vector; also a GPIO pin in Blackfin interface mode.
51 RT input Active-high RAM trigger that sweeps RAM amplitude scaling up; tie to ground or supply if unused.
52 PROFILE2 input Profile select input (active high) that selects one of eight DDS profiles together with PROFILE1 and PROFILE0.
53 PROFILE1 input Profile select input (active high) that selects one of eight DDS profiles together with PROFILE2 and PROFILE0.
54 PROFILE0 input Profile select input (active high) that selects one of eight DDS profiles together with PROFILE2 and PROFILE1.
55 SYNC_CLK output System clock divided by 4 output used to time I/O_UPDATE and profile pin changes.
56 DVDD_I/O (3.3V) power_in 3.3 V digital input/output supply, nominally 3.3 V ±5%.
57 DVDD (1.8V) power_in 1.8 V digital core supply, nominally 1.8 V ±5%.
58 DGND power_in Digital ground.
59 I/O_UPDATE bidirectional Active-high I/O update pin, an input by default that transfers I/O buffer contents to registers on a rising edge, or an output when internal I/O update is active.
60 OSK input Active-high output shift keying input that controls the OSK function; tie high when OSK is not used.
61 NC unconnected Not connected; allow the pin to float.
62 DGND power_in Digital ground.
63 DGND power_in Digital ground.
64 DVDD (1.8V) power_in 1.8 V digital core supply, nominally 1.8 V ±5%.
65 DGND power_in Digital ground.
66 DVDD_I/O (3.3V) power_in 3.3 V digital input/output supply, nominally 3.3 V ±5%.
67 SDIO bidirectional Serial data input/output, bidirectional by default; acts as input only in unidirectional mode.
68 SDO output Serial data output, active only in unidirectional serial mode and must float in bidirectional mode.
69 SCLK input Serial data clock; writes are sampled on the rising edge and readbacks change on the falling edge.
70 CS input Active-low chip select that enables serial clock detection; driving it high makes the device ignore serial data.
71 I/O_RESET input Active-high input that aborts a failed serial I/O cycle; connect to ground when not used.
72 NC unconnected Not connected; allow the pin to float.
73 AGND power_in Analog ground.
74 AVDD (3.3V) power_in 3.3 V analog DAC supply, nominally 3.3 V ±5%.
75 AVDD (3.3V) power_in 3.3 V analog DAC supply, nominally 3.3 V ±5%.
76 AVDD (3.3V) power_in 3.3 V analog DAC supply, nominally 3.3 V ±5%.
77 AVDD (3.3V) power_in 3.3 V analog DAC supply, nominally 3.3 V ±5%.
78 AGND power_in Analog ground.
79 AGND power_in Analog ground.
80 IOUT output Complementary DAC current output source; connect through 50 ohm to AGND.
81 IOUT output DAC current output source; connect through 50 ohm to AGND.
82 AGND power_in Analog ground.
83 AVDD (3.3V) power_in 3.3 V analog DAC supply, nominally 3.3 V ±5%.
84 DAC_RSET output Analog reference pin that sets DAC full-scale current; attach a 10 kohm resistor to AGND.
85 AGND power_in Analog ground.
86 NC unconnected Not connected; allow the pin to float.
87 NC unconnected Not connected; allow the pin to float.
88 AGND power_in Analog ground.
89 AVDD (1.8V) power_in 1.8 V analog supply for the REFCLK input, nominally 1.8 V ±5%.
90 REF_CLK input Analog reference clock input.
91 REF_CLK input Complementary analog reference clock input.
92 AVDD (1.8V) power_in 1.8 V analog supply for the REFCLK input, nominally 1.8 V ±5%.
93 NC unconnected Not connected; allow the pin to float.
94 REFCLK_OUT output Analog reference clock output, with a maximum frequency of 25 MHz and maximum capacitive load of 20 pF.
95 XTAL_SEL input Active-high crystal select input (1.8 V logic) that enables the internal oscillator; connect to AGND if unused.
96 AGND power_in Analog ground.
97 NC unconnected Not connected; allow the pin to float.
98 NC unconnected Not connected; allow the pin to float.
99 NC unconnected Not connected; allow the pin to float.
100 NC unconnected Not connected; allow the pin to float.
101 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TQFP-100-EP(14x14)
Category Data Converters
Pins 101

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
REF_CLK frequency range (REFCLK multiplier disabled) 60 1000 MHz REFCLK Multiplier Disabled 5
REF_CLK frequency range (REFCLK multiplier enabled) 3.2 60 MHz REFCLK multiplier enabled 5
Maximum REFCLK input divider frequency 1500 1900 MHz Full temperature range 5
Minimum REFCLK input divider frequency 25 35 MHz Full temperature range 5
Duty cycle (REFCLK multiplier disabled) 45 55 % REFCLK multiplier disabled 5
Duty cycle (REFCLK multiplier enabled) 40 60 % REFCLK multiplier enabled 5
REF_CLK input level (single-ended) 50 1000 mV p-p Single-ended 5
REF_CLK input level (differential) 100 2000 mV p-p Differential 5
Gain error -10 10 %FS 5
AC voltage compliance range -0.5 0.5 V 5
Full-scale output current 8.6 20 31.6 mA 5
Minimum SCLK pulse width low 4 ns Low 6
Minimum SCLK pulse width high 4 ns High 6
Maximum SCLK rise/fall time 2 ns 6
Minimum data setup time to SCLK 5 ns 6
Minimum data hold time to SCLK 0 ns 6
Maximum data valid time in read mode 11 ns Read mode 6
I/O_UPDATE/PROFILE2 minimum pulse width high 1 SYNC_CLK cycle 6
I/O_UPDATE/PROFILE2 minimum setup time to SYNC_CLK 1.75 ns 6
I/O_UPDATE/PROFILE2 minimum hold time to SYNC_CLK 0 ns 6
Maximum PDCLK frequency 250 MHz 6
Minimum I/Q data setup time to PDCLK 1.75 ns 6
Minimum I/Q data hold time to PDCLK 0 ns 6
Minimum TxENABLE setup time to PDCLK 1.75 ns 6
Minimum TxENABLE hold time to PDCLK 0 ns 6
Minimum reset pulse width high 5 SYSCLK cycles 6
CMOS logic input voltage, logic 1 2 V 7
CMOS logic input voltage, logic 0 0.8 V 7
XTAL_SEL input logic 1 voltage 1.25 V 7
XTAL_SEL input logic 0 voltage 0.6 V 7
CMOS logic output voltage, logic 1 2.8 V 1 mA load 7
CMOS logic output voltage, logic 0 0.4 V 1 mA load 7
AVDD (1.8V), DVDD (1.8V) supplies 2 V 8
AVDD (3.3V), DVDD_I/O (3.3V) supplies 4 V 8
Digital input voltage -0.7 4 V 8
XTAL_SEL voltage -0.7 2.2 V 8
Digital output current 5 mA 8
Storage temperature range -65 150 °C 8
Operating temperature range -40 85 °C 8
Maximum junction temperature 150 °C 8
Lead temperature, soldering 300 °C 10 sec 8
Thermal resistance, junction-to-ambient θJA 22 °C/W 8
Thermal resistance, junction-to-case θJC 2.8 °C/W 8

CAD (KiCad official)

  • Symbol: AD9957BSVZ
  • Footprint: Package_QFP:TQFP-100-1EP_14x14mm_P0.5mm_EP5x5mm
  • 3D model: TQFP-100-EP(14x14) (KiCad packages3D, STEP)
  • 3D model files: ad9957bsvz-etched.step / ad9957bsvz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9957bsvz.step / ad9957bsvz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (61 pp, sha256 48d891dd2d5e7471, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF