AD9912ABCPZ

Analog Devices · Direct Digital Synthesis (DDS) · LFCSP-64(9x9)

AD9912ABCPZ from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DVDD_I/O	power_in	Digital I/O supply, 3.135 V to 3.465 V (3.30 V nominal) per Table 1.
2	DVSS	power_in	Digital ground; connect to ground.
3	DVDD	power_in	Digital core supply, 1.71 V to 1.89 V (1.80 V nominal) per Table 1.
4	DVSS	power_in	Digital ground; connect to ground.
5	DVDD	power_in	Digital core supply, 1.71 V to 1.89 V (1.80 V nominal) per Table 1.
6	DVSS	power_in	Digital ground; connect to ground.
7	DVDD	power_in	Digital core supply, 1.71 V to 1.89 V (1.80 V nominal) per Table 1.
8	DVSS	power_in	Digital ground; connect to ground.
9	S1	bidirectional	3.3 V CMOS start-up configuration pin; configured under program control and has no internal pull-up/pull-down; logic input VIH min 2.0 V and VIL max 0.8 V.
10	S2	bidirectional	3.3 V CMOS start-up configuration pin; configured under program control and has no internal pull-up/pull-down; logic input VIH min 2.0 V and VIL max 0.8 V.
11	AVDD	power_in	Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1).
12	NC	unconnected	No connect; unused pin can be left unconnected.
13	NC	unconnected	No connect; unused pin can be left unconnected.
14	AVDD3	power_in	Analog 3.3 V supply, 3.135 V to 3.465 V per Table 1.
15	NC	unconnected	No connect; unused pin can be left unconnected.
16	NC	unconnected	No connect; unused pin can be left unconnected.
17	NC	unconnected	No connect; unused pin can be left unconnected.
18	NC	unconnected	No connect; unused pin can be left unconnected.
19	AVDD	power_in	Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1).
20	NC	unconnected	No connect; unused pin can be left unconnected.
21	NC	unconnected	No connect; unused pin can be left unconnected.
22	NC	unconnected	No connect; unused pin can be left unconnected.
23	AVDD	power_in	Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1).
24	AVDD	power_in	Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1).
25	AVDD	power_in	Analog supply for the system clock PLL, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1).
26	AVDD	power_in	Analog supply for the system clock PLL, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1); the loop filter connects to this pin.
27	SYSCLK	input	Differential system clock input with internal dc bias; should be ac-coupled except when using a crystal (then tie CLKMODESEL to AVSS and connect the crystal to pins 27 and 28).
28	SYSCLKB	input	Complementary system clock input; use a 0.01 µF capacitor to ground on this pin if pin 27 is driven single-ended.
29	AVDD	power_in	Analog supply for the system clock PLL, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1).
30	AVDD	power_in	Analog supply for the system clock PLL, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1).
31	LOOP_FILTER	output	System clock multiplier loop filter; an external loop filter is required when the PLL is used, and the pin should be pulled to ground through 1 kΩ when the PLL is bypassed.
32	CLKMODESEL	input	1.8 V CMOS clock mode select; set to GND for a crystal on pins 27/28, pull up to 1.8 V for an oscillator or external clock; VIH min 1.4 V and VIL max 0.4 V per Table 1.
33	AVSS	power_in	Analog ground; connect to ground.
34	OUTB	output	Complementary 1.8 V HSTL output.
35	OUT	output	1.8 V HSTL output.
36	AVDD	power_in	Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1).
37	AVDD3	power_in	Analog supply for the CMOS output driver; normally 3.3 V (1.71 V to 3.465 V per Table 1) but can be 1.8 V, and should be powered even if the CMOS driver is not used.
38	OUT_CMOS	output	3.3 V CMOS output; becomes 1.8 V CMOS if pin 37 is set to 1.8 V.
39	AVSS	power_in	Analog ground; connect to ground.
40	FDBK_INB	input	Complementary feedback input, typically ac-coupled to the filtered DAC_OUTB; when used as an ac-coupled input it accepts a differential signal with single-ended swing of at least 400 mV.
41	FDBK_IN	input	Feedback input connected to the filtered DAC_OUT in standard operating mode; differential input resistance 22 kΩ typical and must be ac-coupled.
42	AVDD	power_in	Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1).
43	AVSS	power_in	Analog ground; connect to ground.
44	AVDD	power_in	Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1).
45	AVDD	power_in	Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1).
46	AVDD3	power_in	DAC 3.3 V analog supply, 3.135 V to 3.465 V per Table 1; a ferrite bead should isolate it from other 3.3 V supplies.
47	AVDD3	power_in	DAC 3.3 V analog supply, 3.135 V to 3.465 V per Table 1; a ferrite bead should isolate it from other 3.3 V supplies.
48	DAC_RSET	output	DAC output current setting resistor; connect a resistor (usually 10 kΩ) from this pin to GND.
49	AVDD3	power_in	DAC 3.3 V analog supply, 3.135 V to 3.465 V per Table 1; a ferrite bead should isolate it from other 3.3 V supplies.
50	DAC_OUT	output	DAC output; should be filtered and returned on-chip to FDBK_IN, and has an internal 50 Ω pull-down resistor.
51	DAC_OUTB	output	Complementary DAC output; should be filtered and returned on-chip to FDBK_INB, and has an internal 50 Ω pull-down resistor.
52	AVSS	power_in	Analog ground; connect to ground.
53	AVDD	power_in	Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1); consumes about 40 mA per the power partitioning section.
54	S3	bidirectional	3.3 V CMOS start-up configuration pin; configured under program control and has no internal pull-up/pull-down; logic input VIH min 2.0 V and VIL max 0.8 V.
55	S4	bidirectional	3.3 V CMOS start-up configuration pin; configured under program control and has no internal pull-up/pull-down; logic input VIH min 2.0 V and VIL max 0.8 V.
56	DVSS	power_in	Digital ground; connect to ground.
57	DVSS	power_in	Digital ground; connect to ground.
58	PWRDOWN	input	Active-high full power-down input; with internal 50 kΩ pull-down, logic input VIH min 2.0 V and VIL max 0.8 V.
59	RESET	input	Active-high chip reset; a 10 µs reset pulse is generated internally at power-up, and the pin should be grounded through 10 kΩ if not used.
60	IO_UPDATE	input	A 0-to-1 transition transfers data from the I/O port registers to the control registers; internal 50 kΩ pull-down.
61	CSB	input	Active-low chip select that must be held low during programming; internal 100 kΩ pull-up to 3.3 V and must not be left floating.
62	SDO	output	Serial data output used to read back data; no internal pull-up or pull-down, with VOH min 2.7 V at 1 mA.
63	SDIO	bidirectional	Serial data input/output; carries write data in 3-wire mode and both read and write data in 2-wire mode, with no internal pull-up or pull-down.
64	SCLK	input	Serial programming clock; write data is registered on the rising edge, read data on the falling edge, with internal 50 kΩ pull-down.
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-64(9x9)
Category	ADC/DAC/Data Conversion
Pins	65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Analog Supply Voltage (AVDD)	AVDD			2	V		7
Digital Supply Voltage (DVDD)	DVDD			2	V		7
Digital I/O Supply Voltage (DVDD_I/O)	DVDD_I/O			3.6	V		7
DAC Supply Voltage (AVDD3 Pins)	AVDD3			3.6	V		7
Maximum Digital Input Voltage		-0.5			V		7
Storage Temperature		-65		150	°C		7
Operating Temperature Range		-40		85	°C		7
Lead Temperature (Soldering)				300	°C	10 sec	7
Junction Temperature				150	°C		7
DVDD_I/O supply voltage	DVDD_I/O	3.135	3.3	3.465	V	Pin 1	3
DVDD supply voltage	DVDD	1.71	1.8	1.89	V	Pin 3, Pin 5, Pin 7	3
AVDD3 supply voltage	AVDD3	3.135	3.3	3.465	V	Pin 14, Pin 46, Pin 47, Pin 49	3
AVDD3 supply voltage (CMOS driver supply)	AVDD3	1.71	3.3	3.465	V	Pin 37; typically 3.3 V but can be set to 1.8 V	3
AVDD supply voltage	AVDD	1.71	1.8	1.89	V	Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29, Pin 30, Pin 36, Pin 42, Pin 44, Pin 45, Pin 53	3
AVDD3 supply current	IAVDD3		8	9.6	mA	Pin 37; CMOS output driver at 3.3 V, 50 MHz, with 5 pF load	3
AVDD3 supply current	IAVDD3		26	31	mA	Pin 46, Pin 47, Pin 49; DAC output current source, fS = 1 GSPS	3
Aggregate analog supply current	IAVDD		113	136	mA	Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29, Pin 30, Pin 36, Pin 42, Pin 44, Pin 45; with system clock PLL, HSTL output driver, and S-divider enabled	3
DAC power supply current	IAVDD		40	48	mA	Pin 53; DAC power supply	3
Digital core supply current	IDVDD		205	246	mA	Pin 3, Pin 5, Pin 7; SpurKiller off	3
Digital I/O supply current	IDVDD_I/O		2	3	mA	Digital I/O (varies dynamically)	3
Total power dissipation, DDS only			637	765	mW	Power-on default, except SYSCLK PLL bypassed and CMOS driver off; SYSCLK = 1 GHz; HSTL driver off; spur reduction off; fOUT = 200 MHz	4
Total power dissipation, DDS with spur reduction on			686	823	mW	Same as DDS Only case, except both spur reduction channels on	4
Total power dissipation, DDS with HSTL driver enabled			657	788	mW	Same as DDS Only case, except HSTL driver enabled	4
Total power dissipation, DDS with CMOS driver enabled			729	875	mW	Same as DDS Only case, except CMOS driver and S-divider enabled and at 3.3 V; CMOS fOUT = 50 MHz (S-divider = 4)	4
Total power dissipation, DDS with HSTL and CMOS drivers enabled			747	897	mW	Same as DDS Only case, except both HSTL and CMOS drivers enabled; S-divider = 4; CMOS fOUT = 50 MHz	4
Total power dissipation, DDS with SYSCLK PLL enabled			648	777	mW	Same as DDS Only case, except 25 MHz SYSCLK input and PLL multiplier = 40	4
Total power dissipation, power-down mode			13	16	mW	Using either the power-down and enable register or the PWRDOWN pin	4
Input High Voltage	VIH	2			V	Except Pin 32	3
Input Low Voltage	VIL			0.8	V	Except Pin 32	3
CLKMODESEL Input High Voltage	VIH	1.4			V	Pin 32 only	3
Logic Output High Voltage	VOH	2.7			V	IOH = 1 mA	3
Logic Output Low Voltage	VOL			0.4	V	IOL = 1 mA	3
Full-Scale Output Current		20		31.7	mA	Range depends on DAC RSET resistor	5
Gain Error		-10		10	% FS		5
DCO Frequency Range (1st Nyquist Zone)		0		450	MHz	1st Nyquist zone	5
Voltage Compliance Range (relative to AVSS)		-0.5		0.5	V	Outputs connected to a transformer whose center tap is grounded	6
FDBK_IN Input Frequency Range		10		400	MHz		4
SYSCLK Input Frequency Range (PLL bypassed)		250		1000	MHz	SYSCLK PLL Bypassed; maximum fOUT is 0.4 × fSYSCLK	4
VCO Frequency Range, Low Band		700		810	MHz	Use low VCO band exclusively	5
VCO Frequency Range, Auto Band		810		900	MHz	Use VCO auto band select	5
VCO Frequency Range, High Band		900		1000	MHz	Use high VCO band exclusively	5
Maximum Input Rate of System Clock PFD				200	MHz		5
Crystal Resonator Frequency Range		10		50	MHz	AT cut, fundamental mode resonator	5
HSTL Output Driver Frequency Range		20		725	MHz	See Figure 27 for maximum toggle rate	5
HSTL Differential Output Voltage Swing		1080	1280	1480	mV	Output driver static	4
HSTL Rise Time/Fall Time (20% to 80%)		115		165	ps	100 Ω termination across OUT/OUTB, 2 pF load	5
CMOS Output Driver Frequency Range (3.3 V)		0.008		150	MHz	AVDD3 (Pin 37) = 3.3 V	5
CMOS Output Driver Frequency Range (1.8 V)		0.008		40	MHz	AVDD3 (Pin 37) = 1.8 V	5
CMOS Output Voltage High (VOH)	VOH	2.7			V	IOH = 1 mA, Pin 37 = 3.3 V	4
CMOS Output Voltage Low (VOL)	VOL			0.4	V	IOL = 1 mA, Pin 37 = 3.3 V	4
CMOS Output Voltage High (VOH)	VOH	1.4			V	IOH = 1 mA, Pin 37 = 1.8 V	4
Crystal Motional Resistance		9		100	Ω	25 MHz, 3.2 mm × 2.5 mm AT cut; SYSCLK PLL enabled	4
FDBK_IN Input Resistance (differential)		18	22	26	kΩ	Differential	3
SYSCLK Input Resistance (PLL bypassed)		2.4	2.6	2.9	kΩ	Differential; SYSCLK PLL Bypassed	3
SYSCLK Internally Generated DC Bias Voltage (PLL bypassed)		0.93	1.17	1.38	V	AVSS = 0 V; SYSCLK PLL Bypassed	3
SCLK Clock Rate	1/tCLK	25		50	MHz	Maximum SCLK rate for readback is governed by tDV	6
Thermal Resistance Junction-to-Ambient (64-Lead LFCSP)	θJA		25.2		°C/W	Device soldered in circuit board (worst case)	7
Thermal Resistance Junction-to-Board (64-Lead LFCSP)	θJB		13.9		°C/W		7
Thermal Resistance Junction-to-Case (64-Lead LFCSP)	θJC		1.7		°C/W		7

CAD (KiCad official)

Symbol: AD9912ABCPZ
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)
3D model files: ad9912abcpz-etched.step / ad9912abcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9912abcpz.step / ad9912abcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (38 pp, sha256 4515379905d95bf8, retrieved 2026-10-28, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# AD9912ABCPZ

**Analog Devices** · Direct Digital Synthesis (DDS) · LFCSP-64(9x9)

AD9912ABCPZ from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVDD_I/O | power_in | Digital I/O supply, 3.135 V to 3.465 V (3.30 V nominal) per Table 1. |
| 2 | DVSS | power_in | Digital ground; connect to ground. |
| 3 | DVDD | power_in | Digital core supply, 1.71 V to 1.89 V (1.80 V nominal) per Table 1. |
| 4 | DVSS | power_in | Digital ground; connect to ground. |
| 5 | DVDD | power_in | Digital core supply, 1.71 V to 1.89 V (1.80 V nominal) per Table 1. |
| 6 | DVSS | power_in | Digital ground; connect to ground. |
| 7 | DVDD | power_in | Digital core supply, 1.71 V to 1.89 V (1.80 V nominal) per Table 1. |
| 8 | DVSS | power_in | Digital ground; connect to ground. |
| 9 | S1 | bidirectional | 3.3 V CMOS start-up configuration pin; configured under program control and has no internal pull-up/pull-down; logic input VIH min 2.0 V and VIL max 0.8 V. |
| 10 | S2 | bidirectional | 3.3 V CMOS start-up configuration pin; configured under program control and has no internal pull-up/pull-down; logic input VIH min 2.0 V and VIL max 0.8 V. |
| 11 | AVDD | power_in | Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1). |
| 12 | NC | unconnected | No connect; unused pin can be left unconnected. |
| 13 | NC | unconnected | No connect; unused pin can be left unconnected. |
| 14 | AVDD3 | power_in | Analog 3.3 V supply, 3.135 V to 3.465 V per Table 1. |
| 15 | NC | unconnected | No connect; unused pin can be left unconnected. |
| 16 | NC | unconnected | No connect; unused pin can be left unconnected. |
| 17 | NC | unconnected | No connect; unused pin can be left unconnected. |
| 18 | NC | unconnected | No connect; unused pin can be left unconnected. |
| 19 | AVDD | power_in | Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1). |
| 20 | NC | unconnected | No connect; unused pin can be left unconnected. |
| 21 | NC | unconnected | No connect; unused pin can be left unconnected. |
| 22 | NC | unconnected | No connect; unused pin can be left unconnected. |
| 23 | AVDD | power_in | Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1). |
| 24 | AVDD | power_in | Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1). |
| 25 | AVDD | power_in | Analog supply for the system clock PLL, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1). |
| 26 | AVDD | power_in | Analog supply for the system clock PLL, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1); the loop filter connects to this pin. |
| 27 | SYSCLK | input | Differential system clock input with internal dc bias; should be ac-coupled except when using a crystal (then tie CLKMODESEL to AVSS and connect the crystal to pins 27 and 28). |
| 28 | SYSCLKB | input | Complementary system clock input; use a 0.01 µF capacitor to ground on this pin if pin 27 is driven single-ended. |
| 29 | AVDD | power_in | Analog supply for the system clock PLL, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1). |
| 30 | AVDD | power_in | Analog supply for the system clock PLL, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1). |
| 31 | LOOP_FILTER | output | System clock multiplier loop filter; an external loop filter is required when the PLL is used, and the pin should be pulled to ground through 1 kΩ when the PLL is bypassed. |
| 32 | CLKMODESEL | input | 1.8 V CMOS clock mode select; set to GND for a crystal on pins 27/28, pull up to 1.8 V for an oscillator or external clock; VIH min 1.4 V and VIL max 0.4 V per Table 1. |
| 33 | AVSS | power_in | Analog ground; connect to ground. |
| 34 | OUTB | output | Complementary 1.8 V HSTL output. |
| 35 | OUT | output | 1.8 V HSTL output. |
| 36 | AVDD | power_in | Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1). |
| 37 | AVDD3 | power_in | Analog supply for the CMOS output driver; normally 3.3 V (1.71 V to 3.465 V per Table 1) but can be 1.8 V, and should be powered even if the CMOS driver is not used. |
| 38 | OUT_CMOS | output | 3.3 V CMOS output; becomes 1.8 V CMOS if pin 37 is set to 1.8 V. |
| 39 | AVSS | power_in | Analog ground; connect to ground. |
| 40 | FDBK_INB | input | Complementary feedback input, typically ac-coupled to the filtered DAC_OUTB; when used as an ac-coupled input it accepts a differential signal with single-ended swing of at least 400 mV. |
| 41 | FDBK_IN | input | Feedback input connected to the filtered DAC_OUT in standard operating mode; differential input resistance 22 kΩ typical and must be ac-coupled. |
| 42 | AVDD | power_in | Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1). |
| 43 | AVSS | power_in | Analog ground; connect to ground. |
| 44 | AVDD | power_in | Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1). |
| 45 | AVDD | power_in | Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1). |
| 46 | AVDD3 | power_in | DAC 3.3 V analog supply, 3.135 V to 3.465 V per Table 1; a ferrite bead should isolate it from other 3.3 V supplies. |
| 47 | AVDD3 | power_in | DAC 3.3 V analog supply, 3.135 V to 3.465 V per Table 1; a ferrite bead should isolate it from other 3.3 V supplies. |
| 48 | DAC_RSET | output | DAC output current setting resistor; connect a resistor (usually 10 kΩ) from this pin to GND. |
| 49 | AVDD3 | power_in | DAC 3.3 V analog supply, 3.135 V to 3.465 V per Table 1; a ferrite bead should isolate it from other 3.3 V supplies. |
| 50 | DAC_OUT | output | DAC output; should be filtered and returned on-chip to FDBK_IN, and has an internal 50 Ω pull-down resistor. |
| 51 | DAC_OUTB | output | Complementary DAC output; should be filtered and returned on-chip to FDBK_INB, and has an internal 50 Ω pull-down resistor. |
| 52 | AVSS | power_in | Analog ground; connect to ground. |
| 53 | AVDD | power_in | Analog supply, connect to nominal 1.8 V (1.71 V to 1.89 V per Table 1); consumes about 40 mA per the power partitioning section. |
| 54 | S3 | bidirectional | 3.3 V CMOS start-up configuration pin; configured under program control and has no internal pull-up/pull-down; logic input VIH min 2.0 V and VIL max 0.8 V. |
| 55 | S4 | bidirectional | 3.3 V CMOS start-up configuration pin; configured under program control and has no internal pull-up/pull-down; logic input VIH min 2.0 V and VIL max 0.8 V. |
| 56 | DVSS | power_in | Digital ground; connect to ground. |
| 57 | DVSS | power_in | Digital ground; connect to ground. |
| 58 | PWRDOWN | input | Active-high full power-down input; with internal 50 kΩ pull-down, logic input VIH min 2.0 V and VIL max 0.8 V. |
| 59 | RESET | input | Active-high chip reset; a 10 µs reset pulse is generated internally at power-up, and the pin should be grounded through 10 kΩ if not used. |
| 60 | IO_UPDATE | input | A 0-to-1 transition transfers data from the I/O port registers to the control registers; internal 50 kΩ pull-down. |
| 61 | CSB | input | Active-low chip select that must be held low during programming; internal 100 kΩ pull-up to 3.3 V and must not be left floating. |
| 62 | SDO | output | Serial data output used to read back data; no internal pull-up or pull-down, with VOH min 2.7 V at 1 mA. |
| 63 | SDIO | bidirectional | Serial data input/output; carries write data in 3-wire mode and both read and write data in 2-wire mode, with no internal pull-up or pull-down. |
| 64 | SCLK | input | Serial programming clock; write data is registered on the rising edge, read data on the falling edge, with internal 50 kΩ pull-down. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-64(9x9) |
| Category | ADC/DAC/Data Conversion |
| Pins | 65 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog Supply Voltage (AVDD) | AVDD |  |  | 2 | V |  | 7 |
| Digital Supply Voltage (DVDD) | DVDD |  |  | 2 | V |  | 7 |
| Digital I/O Supply Voltage (DVDD_I/O) | DVDD_I/O |  |  | 3.6 | V |  | 7 |
| DAC Supply Voltage (AVDD3 Pins) | AVDD3 |  |  | 3.6 | V |  | 7 |
| Maximum Digital Input Voltage |  | -0.5 |  |  | V |  | 7 |
| Storage Temperature |  | -65 |  | 150 | °C |  | 7 |
| Operating Temperature Range |  | -40 |  | 85 | °C |  | 7 |
| Lead Temperature (Soldering) |  |  |  | 300 | °C | 10 sec | 7 |
| Junction Temperature |  |  |  | 150 | °C |  | 7 |
| DVDD_I/O supply voltage | DVDD_I/O | 3.135 | 3.3 | 3.465 | V | Pin 1 | 3 |
| DVDD supply voltage | DVDD | 1.71 | 1.8 | 1.89 | V | Pin 3, Pin 5, Pin 7 | 3 |
| AVDD3 supply voltage | AVDD3 | 3.135 | 3.3 | 3.465 | V | Pin 14, Pin 46, Pin 47, Pin 49 | 3 |
| AVDD3 supply voltage (CMOS driver supply) | AVDD3 | 1.71 | 3.3 | 3.465 | V | Pin 37; typically 3.3 V but can be set to 1.8 V | 3 |
| AVDD supply voltage | AVDD | 1.71 | 1.8 | 1.89 | V | Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29, Pin 30, Pin 36, Pin 42, Pin 44, Pin 45, Pin 53 | 3 |
| AVDD3 supply current | IAVDD3 |  | 8 | 9.6 | mA | Pin 37; CMOS output driver at 3.3 V, 50 MHz, with 5 pF load | 3 |
| AVDD3 supply current | IAVDD3 |  | 26 | 31 | mA | Pin 46, Pin 47, Pin 49; DAC output current source, fS = 1 GSPS | 3 |
| Aggregate analog supply current | IAVDD |  | 113 | 136 | mA | Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29, Pin 30, Pin 36, Pin 42, Pin 44, Pin 45; with system clock PLL, HSTL output driver, and S-divider enabled | 3 |
| DAC power supply current | IAVDD |  | 40 | 48 | mA | Pin 53; DAC power supply | 3 |
| Digital core supply current | IDVDD |  | 205 | 246 | mA | Pin 3, Pin 5, Pin 7; SpurKiller off | 3 |
| Digital I/O supply current | IDVDD_I/O |  | 2 | 3 | mA | Digital I/O (varies dynamically) | 3 |
| Total power dissipation, DDS only |  |  | 637 | 765 | mW | Power-on default, except SYSCLK PLL bypassed and CMOS driver off; SYSCLK = 1 GHz; HSTL driver off; spur reduction off; fOUT = 200 MHz | 4 |
| Total power dissipation, DDS with spur reduction on |  |  | 686 | 823 | mW | Same as DDS Only case, except both spur reduction channels on | 4 |
| Total power dissipation, DDS with HSTL driver enabled |  |  | 657 | 788 | mW | Same as DDS Only case, except HSTL driver enabled | 4 |
| Total power dissipation, DDS with CMOS driver enabled |  |  | 729 | 875 | mW | Same as DDS Only case, except CMOS driver and S-divider enabled and at 3.3 V; CMOS fOUT = 50 MHz (S-divider = 4) | 4 |
| Total power dissipation, DDS with HSTL and CMOS drivers enabled |  |  | 747 | 897 | mW | Same as DDS Only case, except both HSTL and CMOS drivers enabled; S-divider = 4; CMOS fOUT = 50 MHz | 4 |
| Total power dissipation, DDS with SYSCLK PLL enabled |  |  | 648 | 777 | mW | Same as DDS Only case, except 25 MHz SYSCLK input and PLL multiplier = 40 | 4 |
| Total power dissipation, power-down mode |  |  | 13 | 16 | mW | Using either the power-down and enable register or the PWRDOWN pin | 4 |
| Input High Voltage | VIH | 2 |  |  | V | Except Pin 32 | 3 |
| Input Low Voltage | VIL |  |  | 0.8 | V | Except Pin 32 | 3 |
| CLKMODESEL Input High Voltage | VIH | 1.4 |  |  | V | Pin 32 only | 3 |
| Logic Output High Voltage | VOH | 2.7 |  |  | V | IOH = 1 mA | 3 |
| Logic Output Low Voltage | VOL |  |  | 0.4 | V | IOL = 1 mA | 3 |
| Full-Scale Output Current |  | 20 |  | 31.7 | mA | Range depends on DAC RSET resistor | 5 |
| Gain Error |  | -10 |  | 10 | % FS |  | 5 |
| DCO Frequency Range (1st Nyquist Zone) |  | 0 |  | 450 | MHz | 1st Nyquist zone | 5 |
| Voltage Compliance Range (relative to AVSS) |  | -0.5 |  | 0.5 | V | Outputs connected to a transformer whose center tap is grounded | 6 |
| FDBK_IN Input Frequency Range |  | 10 |  | 400 | MHz |  | 4 |
| SYSCLK Input Frequency Range (PLL bypassed) |  | 250 |  | 1000 | MHz | SYSCLK PLL Bypassed; maximum fOUT is 0.4 × fSYSCLK | 4 |
| VCO Frequency Range, Low Band |  | 700 |  | 810 | MHz | Use low VCO band exclusively | 5 |
| VCO Frequency Range, Auto Band |  | 810 |  | 900 | MHz | Use VCO auto band select | 5 |
| VCO Frequency Range, High Band |  | 900 |  | 1000 | MHz | Use high VCO band exclusively | 5 |
| Maximum Input Rate of System Clock PFD |  |  |  | 200 | MHz |  | 5 |
| Crystal Resonator Frequency Range |  | 10 |  | 50 | MHz | AT cut, fundamental mode resonator | 5 |
| HSTL Output Driver Frequency Range |  | 20 |  | 725 | MHz | See Figure 27 for maximum toggle rate | 5 |
| HSTL Differential Output Voltage Swing |  | 1080 | 1280 | 1480 | mV | Output driver static | 4 |
| HSTL Rise Time/Fall Time (20% to 80%) |  | 115 |  | 165 | ps | 100 Ω termination across OUT/OUTB, 2 pF load | 5 |
| CMOS Output Driver Frequency Range (3.3 V) |  | 0.008 |  | 150 | MHz | AVDD3 (Pin 37) = 3.3 V | 5 |
| CMOS Output Driver Frequency Range (1.8 V) |  | 0.008 |  | 40 | MHz | AVDD3 (Pin 37) = 1.8 V | 5 |
| CMOS Output Voltage High (VOH) | VOH | 2.7 |  |  | V | IOH = 1 mA, Pin 37 = 3.3 V | 4 |
| CMOS Output Voltage Low (VOL) | VOL |  |  | 0.4 | V | IOL = 1 mA, Pin 37 = 3.3 V | 4 |
| CMOS Output Voltage High (VOH) | VOH | 1.4 |  |  | V | IOH = 1 mA, Pin 37 = 1.8 V | 4 |
| Crystal Motional Resistance |  | 9 |  | 100 | Ω | 25 MHz, 3.2 mm × 2.5 mm AT cut; SYSCLK PLL enabled | 4 |
| FDBK_IN Input Resistance (differential) |  | 18 | 22 | 26 | kΩ | Differential | 3 |
| SYSCLK Input Resistance (PLL bypassed) |  | 2.4 | 2.6 | 2.9 | kΩ | Differential; SYSCLK PLL Bypassed | 3 |
| SYSCLK Internally Generated DC Bias Voltage (PLL bypassed) |  | 0.93 | 1.17 | 1.38 | V | AVSS = 0 V; SYSCLK PLL Bypassed | 3 |
| SCLK Clock Rate | 1/tCLK | 25 |  | 50 | MHz | Maximum SCLK rate for readback is governed by tDV | 6 |
| Thermal Resistance Junction-to-Ambient (64-Lead LFCSP) | θJA |  | 25.2 |  | °C/W | Device soldered in circuit board (worst case) | 7 |
| Thermal Resistance Junction-to-Board (64-Lead LFCSP) | θJB |  | 13.9 |  | °C/W |  | 7 |
| Thermal Resistance Junction-to-Case (64-Lead LFCSP) | θJC |  | 1.7 |  | °C/W |  | 7 |

## CAD (KiCad official)

- Symbol: `AD9912ABCPZ`
- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`
- 3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)
- 3D model files: `ad9912abcpz-etched.step` / `ad9912abcpz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad9912abcpz.step` / `ad9912abcpz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD9912.pdf) (38 pp, sha256 `4515379905d95bf8`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad9912abcpz-datasheet.pdf)