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AD9910BSVZ

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Analog Devices Direct Digital Synthesis (DDS), TQFP-100-EP(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD9910BSVZ

Analog Devices · Direct Digital Synthesis (DDS) · TQFP-100-EP(14x14)

AD9910BSVZ from Analog Devices, in a TQFP-100-EP(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Not connected; allow the pin to float.
2 PLL_LOOP_FILTER passive PLL loop filter compensation pin for the external loop filter components.
3 AVDD (1.8V) power_in Analog core 1.8 V supply, which powers the REFCLK multiplier (PLL) and consumes about 7 mA.
4 AGND power_in Analog ground.
5 AGND power_in Analog ground.
6 AVDD (1.8V) power_in Analog core 1.8 V supply, which can be grouped with the DVDD 1.8 V supply pins.
7 SYNC_IN+ input LVDS synchronization input (rising edge active) from the external master to synchronize internal subclocks.
8 SYNC_IN- input LVDS synchronization input (complement) from the external master to synchronize internal subclocks.
9 SYNC_OUT+ output LVDS synchronization output (rising edge active) from the internal device subclocks to synchronize external slave devices.
10 SYNC_OUT- output LVDS synchronization output (complement) from the internal device subclocks to synchronize external slave devices.
11 DVDD_I/O (3.3V) power_in Digital input/output 3.3 V supply.
12 SYNC_SMP_ERR output Synchronization sample error output, active high, indicating that no valid sync signal was received on SYNC_IN+/SYNC_IN-.
13 DGND power_in Digital ground.
14 MASTER_RESET input Master reset input, active high, which clears all memory elements and sets registers to default values.
15 DVDD_I/O (3.3V) power_in Digital input/output 3.3 V supply.
16 DGND power_in Digital ground.
17 DVDD (1.8V) power_in Digital core 1.8 V supply.
18 EXT_PWR_DWN input External power-down input, active high, which initiates the currently programmed power-down mode; connect to ground if unused.
19 PLL_LOCK output Clock multiplier PLL lock output, active high, indicating the PLL has acquired lock to the reference clock input.
20 NC unconnected Not connected; allow the pin to float.
21 DVDD_I/O (3.3V) power_in Digital input/output 3.3 V supply.
22 DGND power_in Digital ground.
23 DVDD (1.8V) power_in Digital core 1.8 V supply.
24 RAM_SWP_OVR output RAM sweep over output, active high, indicating the RAM sweep profile has completed.
25 D15 input Parallel input bus bit 15 (active high).
26 D14 input Parallel input bus bit 14 (active high).
27 D13 input Parallel input bus bit 13 (active high).
28 DVDD_I/O (3.3V) power_in Digital input/output 3.3 V supply.
29 DGND power_in Digital ground.
30 DVDD (1.8V) power_in Digital core 1.8 V supply.
31 D12 input Parallel input bus bit 12 (active high).
32 D11 input Parallel input bus bit 11 (active high).
33 D10 input Parallel input bus bit 10 (active high).
34 D9 input Parallel input bus bit 9 (active high).
35 D8 input Parallel input bus bit 8 (active high).
36 D7 input Parallel input bus bit 7 (active high).
37 D6 input Parallel input bus bit 6 (active high).
38 D5 input Parallel input bus bit 5 (active high).
39 D4 input Parallel input bus bit 4 (active high).
40 PDCLK output Parallel data clock digital output that provides a timing signal for aligning data at the parallel inputs.
41 TxENABLE input Transmit enable digital input, active high; in burst mode a high indicates new data for transmission, and in continuous mode it remains high.
42 D3 input Parallel input bus bit 3 (active high).
43 D2 input Parallel input bus bit 2 (active high).
44 D1 input Parallel input bus bit 1 (active high).
45 DVDD_I/O (3.3V) power_in Digital input/output 3.3 V supply.
46 DGND power_in Digital ground.
47 DVDD (1.8V) power_in Digital core 1.8 V supply.
48 D0 input Parallel input bus bit 0 (active high).
49 F1 input Modulation format pin 1, a digital input that determines the modulation format.
50 F0 input Modulation format pin 0, a digital input that determines the modulation format.
51 DGND power_in Digital ground.
52 PROFILE2 input Profile select pin 2 (active high) used to select one of eight phase/frequency profiles, with state changes set up on SYNC_CLK.
53 PROFILE1 input Profile select pin 1 (active high) used to select one of eight phase/frequency profiles, with state changes set up on SYNC_CLK.
54 PROFILE0 input Profile select pin 0 (active high) used to select one of eight phase/frequency profiles, with state changes set up on SYNC_CLK.
55 SYNC_CLK output Output clock divided by four, on whose rising edge inputs such as I/O_UPDATE and PROFILE[2:0] need to be set up.
56 DVDD_I/O (3.3V) power_in Digital input/output 3.3 V supply.
57 DVDD (1.8V) power_in Digital core 1.8 V supply.
58 DGND power_in Digital ground.
59 I/O_UPDATE bidirectional Input/output update, active high; a high transfers the contents of the I/O buffers to the internal registers, and it becomes an output when automatic I/O update is enabled.
60 OSK input Output shift keying digital input, active high, controlling the OSK function in manual or automatic mode.
61 DROVER output Digital ramp over output, active high, switching to Logic 1 whenever the digital ramp generator reaches its programmed upper or lower limit.
62 DRCTL input Digital ramp control input, active high, controlling the slope polarity of the digital ramp generator; connect to Logic 0 if unused.
63 DRHOLD input Digital ramp hold input, active high, which stalls the digital ramp generator in its present state; connect to Logic 0 if unused.
64 DVDD (1.8V) power_in Digital core 1.8 V supply.
65 DGND power_in Digital ground.
66 DVDD_I/O (3.3V) power_in Digital input/output 3.3 V supply.
67 SDIO bidirectional Serial data input/output, either bidirectional (default) or input only in unidirectional mode depending on configuration.
68 SDO output Serial data output, active only in unidirectional serial data mode and left floating in bidirectional mode.
69 SCLK input Serial data clock, with the rising edge used for writes and the falling edge used for reads.
70 CS input Chip select, active low; bringing it low enables detection of serial clock edges and bringing it high makes the device ignore the serial data pins.
71 I/O_RESET input Input/output reset, active high, used when a serial I/O communication cycle fails; connect to ground when not used.
72 NC unconnected Not connected; allow the pin to float.
73 AGND power_in Analog ground.
74 AVDD (3.3V) power_in Analog DAC 3.3 V supply.
75 AVDD (3.3V) power_in Analog DAC 3.3 V supply.
76 AVDD (3.3V) power_in Analog DAC 3.3 V supply.
77 AVDD (3.3V) power_in Analog DAC 3.3 V supply.
78 AGND power_in Analog ground.
79 AGND power_in Analog ground.
80 IOUT output Open-drain DAC complementary current-mode analog output, to be connected through a 50 ohm resistor to AGND.
81 IOUT output Open-drain DAC current-mode analog output, to be connected through a 50 ohm resistor to AGND.
82 AGND power_in Analog ground.
83 AVDD (3.3V) power_in Analog DAC 3.3 V supply.
84 DAC_RSET passive Analog reference pin that programs the DAC full-scale reference current, with a 10 kohm resistor attached to AGND.
85 AGND power_in Analog ground.
86 NC unconnected Not connected; allow the pin to float.
87 NC unconnected Not connected; allow the pin to float.
88 AGND power_in Analog ground.
89 AVDD (1.8V) power_in Analog core 1.8 V supply for the REFCLK input, consuming about 15 mA.
90 REF_CLK input Reference clock analog input, driven by an external oscillator or connected to a crystal when the internal oscillator is engaged.
91 REF_CLK input Complementary reference clock analog input.
92 AVDD (1.8V) power_in Analog core 1.8 V supply for the REFCLK input, consuming about 15 mA.
93 NC unconnected Not connected; allow the pin to float.
94 REFCLK_OUT output Crystal output, an analog output.
95 XTAL_SEL input Crystal select input with 1.8 V logic, active high, enabling the internal oscillator for use with a crystal resonator; connect to AGND if unused.
96 AGND power_in Analog ground.
97 NC unconnected Not connected; allow the pin to float.
98 NC unconnected Not connected; allow the pin to float.
99 NC unconnected Not connected; allow the pin to float.
100 NC unconnected Not connected; allow the pin to float.
101 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TQFP-100-EP(14x14)
Category Data Converters
Pins 101

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Full-Scale Output Current 8.6 20 31.6 mA 5
Gain Error -10 10 % FS 5
Voltage Compliance Range -0.5 0.5 V 5
Minimum SCLK Clock Pulse Width Low 4 ns Low 6
Minimum SCLK Clock Pulse Width High 4 ns High 6
Minimum Data Setup Time to SCLK 5 ns 6
Minimum Data Hold Time to SCLK 0 ns 6
Maximum Data Valid Time in Read Mode 11 ns Read mode 6
Maximum SCLK Rise/Fall Time 2 ns 6
Maximum SCLK Frequency 70 Mbps 6
Minimum Setup Time to SYNC_CLK 1.75 ns 6
Minimum Hold Time to SYNC_CLK 0 ns 6
Minimum Profile Toggle Period 2 SYNC_CLK cycles 6
Maximum PDCLK Frequency 250 MHz 6
TxENABLE/Data Setup Time to PDCLK 1.75 ns 6
TxENABLE/Data Hold Time to PDCLK 0 ns 6
Minimum Reset Pulse Width High 5 SYSCLK cycles 6
AVDD (1.8V), DVDD (1.8V) Supplies 2 V 8
AVDD (3.3V), DVDD_I/O (3.3V) Supplies 4 V 8
Digital Input Voltage -0.7 4 V 8
XTAL_SEL Input Voltage -0.7 2.2 V 8
Digital Output Current 5 mA 8
Storage Temperature Range -65 150 °C 8
Operating Temperature Range -40 85 °C 8
Thermal Resistance Junction-to-Ambient θJA 22 °C/W 8
Thermal Resistance Junction-to-Case θJC 2.8 °C/W 8
Maximum Junction Temperature 150 °C 8
Lead Temperature 300 °C 10 sec soldering 8

CAD (KiCad official)

  • Symbol: AD9910BSVZ
  • Footprint: Package_QFP:TQFP-100-1EP_14x14mm_P0.5mm_EP5x5mm
  • 3D model: TQFP-100-EP(14x14) (KiCad packages3D, STEP)
  • 3D model files: ad9910bsvz-etched.step / ad9910bsvz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9910bsvz.step / ad9910bsvz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (64 pp, sha256 e84adc31ccf0b2ff, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF