component
AD9910BSVZ
Public Made by Adomby adom
Analog Devices Direct Digital Synthesis (DDS), TQFP-100-EP(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+172@@ -0,0 +1,172 @@+# AD9910BSVZ++**Analog Devices** · Direct Digital Synthesis (DDS) · TQFP-100-EP(14x14)++AD9910BSVZ from Analog Devices, in a TQFP-100-EP(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NC | unconnected | Not connected; allow the pin to float. |+| 2 | PLL_LOOP_FILTER | passive | PLL loop filter compensation pin for the external loop filter components. |+| 3 | AVDD (1.8V) | power_in | Analog core 1.8 V supply, which powers the REFCLK multiplier (PLL) and consumes about 7 mA. |+| 4 | AGND | power_in | Analog ground. |+| 5 | AGND | power_in | Analog ground. |+| 6 | AVDD (1.8V) | power_in | Analog core 1.8 V supply, which can be grouped with the DVDD 1.8 V supply pins. |+| 7 | SYNC_IN+ | input | LVDS synchronization input (rising edge active) from the external master to synchronize internal subclocks. |+| 8 | SYNC_IN- | input | LVDS synchronization input (complement) from the external master to synchronize internal subclocks. |+| 9 | SYNC_OUT+ | output | LVDS synchronization output (rising edge active) from the internal device subclocks to synchronize external slave devices. |+| 10 | SYNC_OUT- | output | LVDS synchronization output (complement) from the internal device subclocks to synchronize external slave devices. |+| 11 | DVDD_I/O (3.3V) | power_in | Digital input/output 3.3 V supply. |+| 12 | SYNC_SMP_ERR | output | Synchronization sample error output, active high, indicating that no valid sync signal was received on SYNC_IN+/SYNC_IN-. |+| 13 | DGND | power_in | Digital ground. |+| 14 | MASTER_RESET | input | Master reset input, active high, which clears all memory elements and sets registers to default values. |+| 15 | DVDD_I/O (3.3V) | power_in | Digital input/output 3.3 V supply. |+| 16 | DGND | power_in | Digital ground. |+| 17 | DVDD (1.8V) | power_in | Digital core 1.8 V supply. |+| 18 | EXT_PWR_DWN | input | External power-down input, active high, which initiates the currently programmed power-down mode; connect to ground if unused. |+| 19 | PLL_LOCK | output | Clock multiplier PLL lock output, active high, indicating the PLL has acquired lock to the reference clock input. |+| 20 | NC | unconnected | Not connected; allow the pin to float. |+| 21 | DVDD_I/O (3.3V) | power_in | Digital input/output 3.3 V supply. |+| 22 | DGND | power_in | Digital ground. |+| 23 | DVDD (1.8V) | power_in | Digital core 1.8 V supply. |+| 24 | RAM_SWP_OVR | output | RAM sweep over output, active high, indicating the RAM sweep profile has completed. |+| 25 | D15 | input | Parallel input bus bit 15 (active high). |+| 26 | D14 | input | Parallel input bus bit 14 (active high). |+| 27 | D13 | input | Parallel input bus bit 13 (active high). |+| 28 | DVDD_I/O (3.3V) | power_in | Digital input/output 3.3 V supply. |+| 29 | DGND | power_in | Digital ground. |+| 30 | DVDD (1.8V) | power_in | Digital core 1.8 V supply. |+| 31 | D12 | input | Parallel input bus bit 12 (active high). |+| 32 | D11 | input | Parallel input bus bit 11 (active high). |+| 33 | D10 | input | Parallel input bus bit 10 (active high). |+| 34 | D9 | input | Parallel input bus bit 9 (active high). |+| 35 | D8 | input | Parallel input bus bit 8 (active high). |+| 36 | D7 | input | Parallel input bus bit 7 (active high). |+| 37 | D6 | input | Parallel input bus bit 6 (active high). |+| 38 | D5 | input | Parallel input bus bit 5 (active high). |+| 39 | D4 | input | Parallel input bus bit 4 (active high). |+| 40 | PDCLK | output | Parallel data clock digital output that provides a timing signal for aligning data at the parallel inputs. |+| 41 | TxENABLE | input | Transmit enable digital input, active high; in burst mode a high indicates new data for transmission, and in continuous mode it remains high. |+| 42 | D3 | input | Parallel input bus bit 3 (active high). |+| 43 | D2 | input | Parallel input bus bit 2 (active high). |+| 44 | D1 | input | Parallel input bus bit 1 (active high). |+| 45 | DVDD_I/O (3.3V) | power_in | Digital input/output 3.3 V supply. |+| 46 | DGND | power_in | Digital ground. |+| 47 | DVDD (1.8V) | power_in | Digital core 1.8 V supply. |+| 48 | D0 | input | Parallel input bus bit 0 (active high). |+| 49 | F1 | input | Modulation format pin 1, a digital input that determines the modulation format. |+| 50 | F0 | input | Modulation format pin 0, a digital input that determines the modulation format. |+| 51 | DGND | power_in | Digital ground. |+| 52 | PROFILE2 | input | Profile select pin 2 (active high) used to select one of eight phase/frequency profiles, with state changes set up on SYNC_CLK. |+| 53 | PROFILE1 | input | Profile select pin 1 (active high) used to select one of eight phase/frequency profiles, with state changes set up on SYNC_CLK. |+| 54 | PROFILE0 | input | Profile select pin 0 (active high) used to select one of eight phase/frequency profiles, with state changes set up on SYNC_CLK. |+| 55 | SYNC_CLK | output | Output clock divided by four, on whose rising edge inputs such as I/O_UPDATE and PROFILE[2:0] need to be set up. |+| 56 | DVDD_I/O (3.3V) | power_in | Digital input/output 3.3 V supply. |+| 57 | DVDD (1.8V) | power_in | Digital core 1.8 V supply. |+| 58 | DGND | power_in | Digital ground. |+| 59 | I/O_UPDATE | bidirectional | Input/output update, active high; a high transfers the contents of the I/O buffers to the internal registers, and it becomes an output when automatic I/O update is enabled. |+| 60 | OSK | input | Output shift keying digital input, active high, controlling the OSK function in manual or automatic mode. |+| 61 | DROVER | output | Digital ramp over output, active high, switching to Logic 1 whenever the digital ramp generator reaches its programmed upper or lower limit. |+| 62 | DRCTL | input | Digital ramp control input, active high, controlling the slope polarity of the digital ramp generator; connect to Logic 0 if unused. |+| 63 | DRHOLD | input | Digital ramp hold input, active high, which stalls the digital ramp generator in its present state; connect to Logic 0 if unused. |+| 64 | DVDD (1.8V) | power_in | Digital core 1.8 V supply. |+| 65 | DGND | power_in | Digital ground. |+| 66 | DVDD_I/O (3.3V) | power_in | Digital input/output 3.3 V supply. |+| 67 | SDIO | bidirectional | Serial data input/output, either bidirectional (default) or input only in unidirectional mode depending on configuration. |+| 68 | SDO | output | Serial data output, active only in unidirectional serial data mode and left floating in bidirectional mode. |+| 69 | SCLK | input | Serial data clock, with the rising edge used for writes and the falling edge used for reads. |+| 70 | CS | input | Chip select, active low; bringing it low enables detection of serial clock edges and bringing it high makes the device ignore the serial data pins. |+| 71 | I/O_RESET | input | Input/output reset, active high, used when a serial I/O communication cycle fails; connect to ground when not used. |+| 72 | NC | unconnected | Not connected; allow the pin to float. |+| 73 | AGND | power_in | Analog ground. |+| 74 | AVDD (3.3V) | power_in | Analog DAC 3.3 V supply. |+| 75 | AVDD (3.3V) | power_in | Analog DAC 3.3 V supply. |+| 76 | AVDD (3.3V) | power_in | Analog DAC 3.3 V supply. |+| 77 | AVDD (3.3V) | power_in | Analog DAC 3.3 V supply. |+| 78 | AGND | power_in | Analog ground. |+| 79 | AGND | power_in | Analog ground. |+| 80 | IOUT | output | Open-drain DAC complementary current-mode analog output, to be connected through a 50 ohm resistor to AGND. |+| 81 | IOUT | output | Open-drain DAC current-mode analog output, to be connected through a 50 ohm resistor to AGND. |+| 82 | AGND | power_in | Analog ground. |+| 83 | AVDD (3.3V) | power_in | Analog DAC 3.3 V supply. |+| 84 | DAC_RSET | passive | Analog reference pin that programs the DAC full-scale reference current, with a 10 kohm resistor attached to AGND. |+| 85 | AGND | power_in | Analog ground. |+| 86 | NC | unconnected | Not connected; allow the pin to float. |+| 87 | NC | unconnected | Not connected; allow the pin to float. |+| 88 | AGND | power_in | Analog ground. |+| 89 | AVDD (1.8V) | power_in | Analog core 1.8 V supply for the REFCLK input, consuming about 15 mA. |+| 90 | REF_CLK | input | Reference clock analog input, driven by an external oscillator or connected to a crystal when the internal oscillator is engaged. |+| 91 | REF_CLK | input | Complementary reference clock analog input. |+| 92 | AVDD (1.8V) | power_in | Analog core 1.8 V supply for the REFCLK input, consuming about 15 mA. |+| 93 | NC | unconnected | Not connected; allow the pin to float. |+| 94 | REFCLK_OUT | output | Crystal output, an analog output. |+| 95 | XTAL_SEL | input | Crystal select input with 1.8 V logic, active high, enabling the internal oscillator for use with a crystal resonator; connect to AGND if unused. |+| 96 | AGND | power_in | Analog ground. |+| 97 | NC | unconnected | Not connected; allow the pin to float. |+| 98 | NC | unconnected | Not connected; allow the pin to float. |+| 99 | NC | unconnected | Not connected; allow the pin to float. |+| 100 | NC | unconnected | Not connected; allow the pin to float. |+| 101 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | TQFP-100-EP(14x14) |+| Category | Data Converters |+| Pins | 101 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Full-Scale Output Current | | 8.6 | 20 | 31.6 | mA | | 5 |+| Gain Error | | -10 | | 10 | % FS | | 5 |+| Voltage Compliance Range | | -0.5 | | 0.5 | V | | 5 |+| Minimum SCLK Clock Pulse Width Low | | 4 | | | ns | Low | 6 |+| Minimum SCLK Clock Pulse Width High | | 4 | | | ns | High | 6 |+| Minimum Data Setup Time to SCLK | | 5 | | | ns | | 6 |+| Minimum Data Hold Time to SCLK | | 0 | | | ns | | 6 |+| Maximum Data Valid Time in Read Mode | | | | 11 | ns | Read mode | 6 |+| Maximum SCLK Rise/Fall Time | | | | 2 | ns | | 6 |+| Maximum SCLK Frequency | | | | 70 | Mbps | | 6 |+| Minimum Setup Time to SYNC_CLK | | 1.75 | | | ns | | 6 |+| Minimum Hold Time to SYNC_CLK | | 0 | | | ns | | 6 |+| Minimum Profile Toggle Period | | 2 | | | SYNC_CLK cycles | | 6 |+| Maximum PDCLK Frequency | | | | 250 | MHz | | 6 |+| TxENABLE/Data Setup Time to PDCLK | | 1.75 | | | ns | | 6 |+| TxENABLE/Data Hold Time to PDCLK | | 0 | | | ns | | 6 |+| Minimum Reset Pulse Width High | | 5 | | | SYSCLK cycles | | 6 |+| AVDD (1.8V), DVDD (1.8V) Supplies | | | | 2 | V | | 8 |+| AVDD (3.3V), DVDD_I/O (3.3V) Supplies | | | | 4 | V | | 8 |+| Digital Input Voltage | | -0.7 | | 4 | V | | 8 |+| XTAL_SEL Input Voltage | | -0.7 | | 2.2 | V | | 8 |+| Digital Output Current | | | | 5 | mA | | 8 |+| Storage Temperature Range | | -65 | | 150 | °C | | 8 |+| Operating Temperature Range | | -40 | | 85 | °C | | 8 |+| Thermal Resistance Junction-to-Ambient | θJA | | | 22 | °C/W | | 8 |+| Thermal Resistance Junction-to-Case | θJC | | | 2.8 | °C/W | | 8 |+| Maximum Junction Temperature | | | | 150 | °C | | 8 |+| Lead Temperature | | | | 300 | °C | 10 sec soldering | 8 |++## CAD (KiCad official)++- Symbol: `AD9910BSVZ`+- Footprint: `Package_QFP:TQFP-100-1EP_14x14mm_P0.5mm_EP5x5mm`+- 3D model: TQFP-100-EP(14x14) (KiCad packages3D, STEP)+- 3D model files: `ad9910bsvz-etched.step` / `ad9910bsvz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad9910bsvz.step` / `ad9910bsvz.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD9910.pdf) (64 pp, sha256 `e84adc31ccf0b2ff`, retrieved 2026-10-28, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ad9910bsvz-datasheet.pdf)
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ad9910bsvz.glbadded⋯ 1 unchanged line ⋯
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pin="MASTER_RESET" pad="14"/>+ <connect gate="G$1" pin="DVDD_I/O_3.3V@2" pad="15"/>+ <connect gate="G$1" pin="DGND@2" pad="16"/>+ <connect gate="G$1" pin="DVDD_1.8V" pad="17"/>+ <connect gate="G$1" pin="EXT_PWR_DWN" pad="18"/>+ <connect gate="G$1" pin="PLL_LOCK" pad="19"/>+ <connect gate="G$1" pin="NC@2" pad="20"/>+ <connect gate="G$1" pin="DVDD_I/O_3.3V@3" pad="21"/>+ <connect gate="G$1" pin="DGND@3" pad="22"/>+ <connect gate="G$1" pin="DVDD_1.8V@2" pad="23"/>+ <connect gate="G$1" pin="RAM_SWP_OVR" pad="24"/>+ <connect gate="G$1" pin="D15" pad="25"/>+ <connect gate="G$1" pin="D14" pad="26"/>+ <connect gate="G$1" pin="D13" pad="27"/>+ <connect gate="G$1" pin="DVDD_I/O_3.3V@4" pad="28"/>+ <connect gate="G$1" pin="DGND@4" pad="29"/>+ <connect gate="G$1" pin="DVDD_1.8V@3" pad="30"/>+ <connect gate="G$1" pin="D12" pad="31"/>+ <connect gate="G$1" pin="D11" pad="32"/>+ <connect gate="G$1" pin="D10" pad="33"/>+ <connect gate="G$1" pin="D9" pad="34"/>+ <connect gate="G$1" pin="D8" pad="35"/>+ <connect gate="G$1" pin="D7" pad="36"/>+ <connect gate="G$1" pin="D6" pad="37"/>+ <connect gate="G$1" pin="D5" pad="38"/>+ <connect gate="G$1" pin="D4" pad="39"/>+ <connect gate="G$1" pin="PDCLK" pad="40"/>+ <connect gate="G$1" pin="TxENABLE" pad="41"/>+ <connect gate="G$1" pin="D3" pad="42"/>+ <connect gate="G$1" pin="D2" pad="43"/>+ <connect gate="G$1" pin="D1" pad="44"/>+ <connect gate="G$1" pin="DVDD_I/O_3.3V@5" pad="45"/>+ <connect gate="G$1" pin="DGND@5" pad="46"/>+ <connect gate="G$1" pin="DVDD_1.8V@4" pad="47"/>+ <connect gate="G$1" pin="D0" pad="48"/>+ <connect gate="G$1" pin="F1" pad="49"/>+ <connect gate="G$1" pin="F0" pad="50"/>+ <connect gate="G$1" pin="DGND@6" pad="51"/>+ <connect gate="G$1" pin="EP" pad="101"/>+ <connect gate="G$1" pin="NC@3" pad="100"/>+ <connect gate="G$1" pin="NC@4" pad="99"/>+ <connect gate="G$1" pin="NC@5" pad="98"/>+ <connect gate="G$1" pin="NC@6" pad="97"/>+ <connect gate="G$1" pin="AGND@3" pad="96"/>+ <connect gate="G$1" pin="XTAL_SEL" pad="95"/>+ <connect gate="G$1" pin="REFCLK_OUT" pad="94"/>+ <connect gate="G$1" pin="NC@7" pad="93"/>+ <connect gate="G$1" pin="AVDD_1.8V@3" pad="92"/>+ <connect gate="G$1" pin="REF_CLK" pad="91"/>+ <connect gate="G$1" pin="REF_CLK@2" pad="90"/>+ <connect gate="G$1" pin="AVDD_1.8V@4" pad="89"/>+ <connect gate="G$1" pin="AGND@4" pad="88"/>+ <connect gate="G$1" pin="NC@8" pad="87"/>+ <connect gate="G$1" pin="NC@9" pad="86"/>+ <connect gate="G$1" pin="AGND@5" pad="85"/>+ <connect gate="G$1" pin="DAC_RSET" pad="84"/>+ <connect gate="G$1" pin="AVDD_3.3V" pad="83"/>+ <connect gate="G$1" pin="AGND@6" pad="82"/>+ <connect gate="G$1" pin="IOUT" pad="81"/>+ <connect gate="G$1" pin="IOUT@2" pad="80"/>+ <connect gate="G$1" pin="AGND@7" pad="79"/>+ <connect gate="G$1" pin="AGND@8" pad="78"/>+ <connect gate="G$1" pin="AVDD_3.3V@2" pad="77"/>+ <connect gate="G$1" pin="AVDD_3.3V@3" pad="76"/>+ <connect gate="G$1" pin="AVDD_3.3V@4" pad="75"/>+ <connect gate="G$1" pin="AVDD_3.3V@5" pad="74"/>+ <connect gate="G$1" pin="AGND@9" pad="73"/>+ <connect gate="G$1" pin="NC@10" pad="72"/>+ <connect gate="G$1" pin="I/O_RESET" pad="71"/>+ <connect gate="G$1" pin="CS" pad="70"/>+ <connect gate="G$1" pin="SCLK" pad="69"/>+ <connect gate="G$1" pin="SDO" pad="68"/>+ <connect gate="G$1" pin="SDIO" pad="67"/>+ <connect gate="G$1" pin="DVDD_I/O_3.3V@6" pad="66"/>+ <connect gate="G$1" pin="DGND@7" pad="65"/>+ <connect gate="G$1" pin="DVDD_1.8V@5" pad="64"/>+ <connect gate="G$1" pin="DRHOLD" pad="63"/>+ <connect gate="G$1" pin="DRCTL" pad="62"/>+ <connect gate="G$1" pin="DROVER" pad="61"/>+ <connect gate="G$1" pin="OSK" pad="60"/>+ <connect gate="G$1" pin="I/O_UPDATE" pad="59"/>+ <connect gate="G$1" pin="DGND@8" pad="58"/>+ <connect gate="G$1" pin="DVDD_1.8V@6" pad="57"/>+ <connect gate="G$1" pin="DVDD_I/O_3.3V@7" pad="56"/>+ <connect gate="G$1" pin="SYNC_CLK" pad="55"/>+ <connect gate="G$1" pin="PROFILE0" pad="54"/>+ <connect gate="G$1" pin="PROFILE1" pad="53"/>+ <connect gate="G$1" pin="PROFILE2" pad="52"/>+ </connects>+ <technologies><technology name=""/></technologies>+ </device>+ </devices>+</deviceset>+</devicesets>+</library>+</drawing>+</eagle>
ad9910bsvz.stepadded+21187@@ -0,0 +1,31060 @@+ISO-10303-21;+HEADER;+/* TQFP-100-1EP_14x14mm_P0.5mm_EP5x5mm.step 3D STEP model for use in ECAD systems+ * Copyright (C) 2025, KiCAD+ *+ * This work is licensed under the+ * [Creative Commons CC-BY-SA 4.0 License](https://creativecommons.org/licenses/by-sa/4.0/legalcode),+ * with the following exception:+ *+ * To the extent that the creation of electronic designs that use 'Licensed Material' can be+ * considered to be 'Adapted Material', then the copyright holder waives article 3 of the license+ * with respect to these designs and any generated files which use data provided as part of the+ * 'Licensed Material'.+ *+ * You are free to use the library data in your own projects without the obligation to share your+ * project files under this or any other license agreement. However, if you wish to distribute+ * these libraries, or parts thereof (including in modified form) as a collection then the exception+ * above does not apply. Please refer to+ * https://gitlab.com/kicad/libraries/kicad-packages3D/-/blob/master/LICENSE.md for further clarification+ * of the exception.+ *+ * Disclaimer of Warranties and Limitation of Liability.+ * These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied.+ * USE 3D CAD DATA AT YOUR OWN RISK+ * DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.+ */++FILE_DESCRIPTION(+/* description */ ('model of TQFP-100-1EP_14x14mm_P0.5mm_EP5x5mm'),+/* implementation_level */ '2;1');++FILE_NAME(+/* name */ 'TQFP-100-1EP_14x14mm_P0.5mm_EP5x5mm.step',+/* time_stamp */ '1970-01-01T00:00:00',+/* author */ ('KiCAD','kicad'),+/* organization */ ('OCCT'),+/* preprocessor_version */ '',+/* originating_system */ 'KiCAD',+/* authorisation */ '');++FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));+ENDSEC;++DATA;+#1=APPLICATION_PROTOCOL_DEFINITION('international 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BOUNDED_SURFACE() B_SPLINE_SURFACE(2,2,((#33,#34,#35,#36,#37),(#326,#327,#328,#329,#330),(#303,#304,#305,#306,#307)),.UNSPECIFIED.,.F.,.F.,.F.) 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B_SPLINE_SURFACE_WITH_KNOTS((3,3),(3,1,1,3),(0.,0.206784146731),(-0.291343960576,-3.998243288843E-02,0.166801713843,0.418163241531),.UNSPECIFIED.) GEOMETRIC_REPRESENTATION_ITEM() RATIONAL_B_SPLINE_SURFACE(((1.,1.,1.,1.,1.),(0.781002645201,0.781002645201,0.781002645201,0.781002645201,0.781002645201),(1.,1.,1.,1.,1.))) REPRESENTATION_ITEM('') SURFACE() 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