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AD9864BCPZ

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Analog Devices RF Chips, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD9864BCPZ

Analog Devices · RF Chips · LFCSP-48(7x7)

AD9864BCPZ from Analog Devices, in a LFCSP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MXOP output Mixer output, positive; the open-collector mixer outputs drive an external differential LC resonant tank tuned to the ADC IF.
2 MXON output Mixer output, negative; the open-collector mixer outputs drive an external differential LC resonant tank tuned to the ADC IF.
3 GNDF power_in Ground for the front end of the ADC.
4 IF2N input Second IF input to the ADC, negative.
5 IF2P input Second IF input to the ADC, positive.
6 VDDF power_in Positive supply for the front end of the ADC.
7 GCP passive Filter capacitor for ADC full-scale control.
8 GCN power_in Ground reference for full-scale control.
9 VDDA power_in Positive supply for the ADC back end.
10 GNDA power_in Ground for the ADC back end.
11 VREFP passive Positive voltage reference for the ADC.
12 VREFN passive Negative voltage reference for the ADC.
13 RREF passive Reference resistor; requires 100 kΩ to GNDA.
14 VDDQ power_in Positive supply for the clock synthesizer charge pump.
15 IOUTC output Clock synthesizer charge pump output current.
16 GNDQ power_in Ground for the clock synthesizer charge pump.
17 VDDC power_in Positive supply for the clock synthesizer.
18 GNDC power_in Ground for the clock synthesizer.
19 CLKP input Sampling clock input and clock VCO tank, positive.
20 CLKN input Sampling clock input and clock VCO tank, negative.
21 GNDS power_in Substrate ground.
22 GNDD power_in Ground for digital functions.
23 PC input Clock input for the SPI port; read on rising edges for instruction header.
24 PD bidirectional Data I/O for the SPI port; becomes input-only in 4-wire SPI mode.
25 PE input Enable input for the SPI port; active low during a transfer.
26 VDDD power_in Positive supply for internal digital circuitry.
27 VDDH power_in Positive supply for the digital interface.
28 CLKOUT output Clock output for the SSI port.
29 DOUTA output Data output for the SSI port.
30 DOUTB tri_state Data output for the SSI port (inverted) or SPI port; can be three-stated via register 0x3B.
31 FS bidirectional Frame sync for the SSI port; three-stated by default per the SSICRA register default.
32 GNDH power_in Ground for the digital interface.
33 SYNCB input Active-low input that resets the SSI and decimator counters; connect to VDDH if unused.
34 GNDS power_in Substrate ground.
35 FREF input Reference frequency input for both synthesizers.
36 GNDL power_in Ground for the LO synthesizer.
37 GNDP power_in Ground for the LO synthesizer charge pump.
38 IOUTL output LO synthesizer charge pump output current.
39 VDDP power_in Positive supply for the LO synthesizer charge pump.
40 VDDL power_in Positive supply for the LO synthesizer.
41 CXVM passive External filter capacitor; DC output of the LNA.
42 LON input LO input to the mixer and LO synthesizer, negative.
43 LOP input LO input to the mixer and LO synthesizer, positive.
44 CXVL passive External bypass capacitor for the LNA power supply.
45 GNDI power_in Ground for the mixer and LNA.
46 CXIF passive External capacitor for the mixer V-I converter bias.
47 IFIN input First IF input to the LNA.
48 VDDI power_in Positive supply for the LNA and mixer.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-48(7x7)
Category RF & Radio
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
SSB Noise Figure at Minimum VGA Attenuation 7.5 9.5 dB Full temp; AGC with DVGA enabled; measured in 10 kHz bandwidth 3
SSB Noise Figure at Maximum VGA Attenuation 13 dB Full temp; AGC with DVGA enabled; measured in 10 kHz bandwidth 3
Dynamic Range with AGC Enabled 91 95 dB Full temp; AGC with DVGA enabled; measured in 10 kHz bandwidth 3
IF Input Clip Point at Maximum VGA Attenuation -20 -19 dBm Full temp 3
IF Input Clip Point at Minimum VGA Attenuation -32 -31 dBm Full temp 3
Input Third-Order Intercept IIP3 -12 -7 dBm Full temp 3
Gain Variation over Temperature 0.7 2 dB Full temp 3
Maximum RF and LO Frequency Range 300 500 MHz Full temp 3
LO Input Frequency 7.75 300 MHz Full temp 3
LO Input Amplitude 0.3 2 V p-p Full temp 3
FREF Frequency (for Sinusoidal Input Only) 8 26 MHz Full temp 3
FREF Input Amplitude 0.3 3 V p-p Full temp 3
FREF Slew Rate 7.5 V/µs Full temp 3
Minimum Charge Pump Current at 5 V (LO synthesizer) 0.67 mA Full temp; programmable in 0.67 mA steps 3
Maximum Charge Pump Current at 5 V (LO synthesizer) 5.3 mA Full temp 3
CLK Input Frequency 13 26 MHz Full temp 3
CLK Input Amplitude 0.3 V p-p Full temp 3
Minimum Charge Pump Output Current (CLK synthesizer) 0.67 mA Full temp; programmable in 0.67 mA steps 3
Maximum Charge Pump Output Current (CLK synthesizer) 5.3 mA Full temp 3
Clock Frequency (fCLK) fCLK 13 26 MHz Full temp 3
Analog Supply Voltage VDDA, VDDF, VDDI 2.7 3 3.6 V Full temp 3
Digital Supply Voltage VDDD, VDDC, VDDL 2.7 3 3.6 V Full temp 3
Interface Supply Voltage VDDH 1.8 3.6 V VDDH must be less than VDDD + 0.5 V 3
Charge Pump Supply Voltage VDDP, VDDQ 2.7 5 5.5 V Full temp 3
Total Current, Operation Mode 17 mA Clock VCO off; additional 0.7 mA with VGA at maximum attenuation 4
Total Current, Standby 0.01 mA 4
Operating Temperature Range -40 85 °C 4
Decimation Factor 48 960 Programmable in steps of 48 or 60 4
Decimator Pass-Band Gain Variation 1.2 dB 4
Decimator Alias Attenuation 88 dBm 4
PC Clock Frequency (SPI read) 10 MHz See Figure 30 4
PC Clock Period (SPI read) tCLK 100 ns See Figure 30 4
PC Clock Frequency (SPI write) 10 MHz See Figure 29 4
PC Clock Period (SPI write) tCLK 100 ns See Figure 29 4
PC to PD (or DOUTB) Data Valid Time tDV 3 ns See Figure 29 4
PE to PD Output Valid to High-Z tEZ 8 ns See Figure 29 4
CLKOUT Frequency 0.867 26 MHz See Figure 33 4
CLKOUT Period tCLK 38.4 1153 ns 4
CLKOUT Duty Cycle tHI, tLOW 33 50 67 ns 4
CLKOUT to FS Valid Time tV -1 1 ns 4
CLKOUT to DOUT Data Valid Time tDV -1 1 ns 5
Logic 0 Voltage (CMOS output) VOL 0.2 V IOL = 1 mA; specification also depends on drive strength setting 5
Logic 1 Current (CMOS input) IIH 10 µA 5
Logic 0 Current (CMOS input) IIL 10 µA 5
Supply voltage vs. ground (VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI) VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI -0.3 4 V With respect to GNDF, GNDA, GNDC, GNDD, GNDH, GNDL, GNDI, GNDS 6
Supply voltage differential between supply pins VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI -4 4 V With respect to VDDR, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI 6
Charge pump supply voltage vs. ground (VDDP, VDDQ) VDDP, VDDQ -0.3 6 V With respect to GNDP, GNDQ 6
Ground pin differential -0.3 0.3 V Ground pins with respect to each other 6
Mixer and LNA pins vs. GNDH MXOP, MXON, LOP, LON, IFIN, CXIF, CXVL, CXVM -0.3 V With respect to GNDH; max is VDDI + 0.3 V 6
Digital interface pins vs. GNDH PC, PD, PE, CLKOUT, DOUTA, DOUTB, FS, SYNCB -0.3 V With respect to GNDH; max is VDDH + 0.3 V 6
ADC front-end pins vs. GNDF IF2N, IF2P, GCP, GCN -0.3 V With respect to GNDF; max is VDDF + 0.3 V 6
Reference pins vs. GNDA VFEFP, VREGN, RREF -0.3 V With respect to GNDA; max is VDDA + 0.3 V 6
Clock synthesizer charge pump output vs. GNDQ IOUTC -0.3 V With respect to GNDQ; max is VDDQ + 0.3 V 6
LO synthesizer charge pump output vs. GNDP IOUTL -0.3 V With respect to GNDP; max is VDDP + 0.3 V 6
Clock input pins vs. GNDC CLKP, CLKN -0.3 V With respect to GNDC; max is VDDC + 0.3 V 6
Reference frequency input vs. GNDL FREF -0.3 V With respect to GNDL; max is VDDL + 0.3 V 6
Maximum Junction Temperature 150 °C 6
Storage Temperature -65 150 °C 6
Maximum Lead Temperature 300 °C 6
Thermal Resistance, Junction-to-Ambient (48-Lead LFCSP) θJA 29.5 °C/W Worst-case; device soldered in circuit board 6

CAD (KiCad official)

  • Symbol: AD9864BCPZ
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: LFCSP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ad9864bcpz-etched.step / ad9864bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9864bcpz.step / ad9864bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (45 pp, sha256 930d62ef6bf7a258, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF