AD9834BRUZ

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  "type": "component",
  "slug": "ad9834bruz",
  "title": "AD9834BRUZ",
  "brief": "Analog Devices Direct Digital Synthesis (DDS), TSSOP-20. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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    "data acquisition",
    "ad9834bruz"
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  "component": {
    "mpn": "AD9834BRUZ",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-20",
    "pin_count": 20,
    "category": "Data Acquisition",
    "subcategory": "Direct Digital Synthesis (DDS)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886866989101056",
    "parts": {
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      "footprint": "ad9834bruz.kicad_mod",
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    "pins": [
      {
        "number": "1",
        "name": "FS ADJUST",
        "type": "passive",
        "description": "Full-scale adjust control. An external resistor R_SET (typ 6.8 kΩ) is connected from this pin to AGND to set the DAC full-scale output current: IOUT_FS = 18 x FSADJUST/R_SET, with FSADJUST = 1.15 V nominal."
      },
      {
        "number": "2",
        "name": "REFOUT",
        "type": "output",
        "description": "Voltage reference output. The AD9834 provides an internal 1.20 V reference on this pin. REFOUT output impedance is typically 1 kΩ (as source). Higher impedance when sinking."
      },
      {
        "number": "3",
        "name": "COMP",
        "type": "passive",
        "description": "DAC bias pin. Used for decoupling the DAC bias voltage."
      },
      {
        "number": "4",
        "name": "AVDD",
        "type": "power_in",
        "description": "Positive analog supply, 2.3 V to 5.5 V. Decouple with a 0.1 µF capacitor to AGND."
      },
      {
        "number": "5",
        "name": "DVDD",
        "type": "power_in",
        "description": "Positive digital supply, 2.3 V to 5.5 V. Decouple with a 0.1 µF capacitor to DGND."
      },
      {
        "number": "6",
        "name": "CAP/2.5V",
        "type": "passive",
        "description": "Internal digital core 2.5 V regulator node. When DVDD > 2.7 V, an on-chip regulator generates 2.5 V for digital logic from DVDD; decouple with a typical 100 nF capacitor from CAP/2.5V to DGND. If DVDD ≤ 2.7 V, tie CAP/2.5V directly to DVDD."
      },
      {
        "number": "7",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground return."
      },
      {
        "number": "8",
        "name": "MCLK",
        "type": "input",
        "description": "Digital master clock input. The DDS output frequency is a binary fraction of MCLK; both output frequency accuracy and phase noise are determined by this clock. Max 75 MHz."
      },
      {
        "number": "9",
        "name": "FSELECT",
        "type": "input",
        "description": "Frequency select input. Controls which frequency register (FREQ0 or FREQ1) is used in the phase accumulator. Can be overridden by control bit FSEL. If FSEL is used, FSELECT should be tied to CMOS high or low."
      },
      {
        "number": "10",
        "name": "PSELECT",
        "type": "input",
        "description": "Phase select input. Controls which phase register (PHASE0 or PHASE1) is added to the phase accumulator output. Can be overridden by control bit PSEL. If PSEL is used, PSELECT should be tied to CMOS high or low."
      },
      {
        "number": "11",
        "name": "RESET",
        "type": "input",
        "description": "Active-high digital reset input. Resets appropriate internal registers to 0, providing an analog output of midscale. RESET does not affect any of the addressable registers."
      },
      {
        "number": "12",
        "name": "SLEEP",
        "type": "input",
        "description": "Active-high digital input. When high, the DAC is powered down. Functionally identical to control-register bit SLEEP12."
      },
      {
        "number": "13",
        "name": "SDATA",
        "type": "input",
        "description": "Serial data input. 16-bit serial data words are applied to this input."
      },
      {
        "number": "14",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input. Data is clocked into the AD9834 on each SCLK falling edge. Max 40 MHz."
      },
      {
        "number": "15",
        "name": "FSYNC",
        "type": "input",
        "description": "Active-low control (frame sync) input. Frames a serial data word transfer; when FSYNC goes low, the device is alerted that a new data word is being loaded."
      },
      {
        "number": "16",
        "name": "SIGN BIT OUT",
        "type": "output",
        "description": "Logic output. The comparator output is available on this pin, or the MSB of the NCO can be output. Enabled by setting control-bit OPBITEN = 1. Bit SIGN/PIB selects whether the comparator output or the NCO MSB is driven out."
      },
      {
        "number": "17",
        "name": "VIN",
        "type": "input",
        "description": "Comparator input. The filtered sinusoidal DAC output can be applied to VIN to produce a square wave. When control bits OPBITEN=1 and SIGN/PIB=1, the comparator input is connected to VIN."
      },
      {
        "number": "18",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground return."
      },
      {
        "number": "19",
        "name": "IOUT",
        "type": "output",
        "description": "Current output of the 10-bit DAC. A nominal 200 Ω external load resistor should be connected between IOUT and AGND. A 20 pF capacitor to AGND is also recommended to help suppress clock feedthrough. Full-scale current typically 3 mA."
      },
      {
        "number": "20",
        "name": "IOUTB",
        "type": "output",
        "description": "Complementary current output. Can be connected to AGND via a nominal 200 Ω load resistor, or tied directly to AGND."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886866989101056",
        "pages": 36,
        "sha256": "8fdc5082ce1704cb",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 20,
        "described": 20,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "seat": "z = 0",
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "97339947f3a7196470ec2f1d9f9b92bb2fc2ab66ad53be0cf105192585ef3c9a",
        "checked": "2026-10-07",
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        "units": "mm",
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  },
  "metadata": {
    "specs": {
      "Manufacturer": "Analog Devices",
      "Package": "TSSOP-20",
      "Category": "Data Acquisition",
      "Pins": "20"
    }
  },
  "variants": [
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      "mpn": "AD9834BRUZ",
      "kind": "packaging"
    },
    {
      "mpn": "AD9834BRUZCRUZ",
      "kind": "packaging"
    },
    {
      "mpn": "AD9834BRUZCRU",
      "kind": "packaging"
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  "sections": [
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  "discovery_triggers": [
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  "discovery_pitch": "AD9834BRUZ (Analog Devices) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
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  "updated_at": "2026-09-24T15:46:39.780Z"
}