main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers ad9833wbrmz-reel: viewers · Ray 1d ago
ad9833wbrmz-reel-etched.glb Publish 0.1.0 · Ray 1d ago
ad9833wbrmz-reel-etched.step ad9833wbrmz-reel: factory component page (tier=mfr) · Ray 1d ago
ad9833wbrmz-reel-hero.glb ad9833wbrmz-reel: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
ad9833wbrmz-reel-hero.overlay.json Publish 0.1.0 · Ray 1d ago
ad9833wbrmz-reel.glb Publish 0.1.0 · Ray 1d ago
ad9833wbrmz-reel.kicad_mod Publish 0.1.0 · Ray 1d ago
ad9833wbrmz-reel.kicad_sym Publish 0.1.0 · Ray 1d ago
ad9833wbrmz-reel.lbr Publish 0.1.0 · Ray 1d ago
ad9833wbrmz-reel.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier mfr, 10 pins · Ray 1d ago

AD9833WBRMZ-REEL

Analog Devices · Direct Digital Synthesis (DDS) · MSOP-10

AD9833WBRMZ-REEL from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COMP passive DAC bias pin used for decoupling the DAC bias voltage.
2 VDD power_in Positive power supply for the analog and digital interface sections, which can range from 2.3 V to 5.5 V and should be decoupled to AGND with 0.1 µF and 10 µF capacitors.
3 CAP/2.5V passive Decoupled to DGND with 100 nF typical; it is generated from VDD by an on-board regulator when VDD exceeds 2.7 V, and must be tied directly to VDD when VDD is 2.7 V or less.
4 DGND power_in Digital ground.
5 MCLK input Digital clock input from which DDS output frequencies are derived as a binary fraction, setting output frequency accuracy and phase noise.
6 SDATA input Serial data input to which the 16-bit serial data word is applied.
7 SCLK input Serial clock input; data is clocked into the AD9833 on each falling edge of SCLK.
8 FSYNC input Active-low frame synchronization input; taking it low signals that a new word is being loaded into the device.
9 AGND power_in Analog ground.
10 VOUT output Analog and digital voltage output with an on-board 200 Ω resistor, so no external load resistor is required.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-10
Category ADC/DAC/Data Conversion
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD VDD 2.3 5.5 V fMCLK = 25 MHz, fOUT = fMCLK/4096 3
IDD supply current IDD 4.5 5.5 mA fMCLK = 25 MHz, fOUT = fMCLK/4096; IDD code dependent; see Figure 7 3
Signal-to-Noise Ratio SNR 54 60 dB AD9833WBRMZ-REEL, fMCLK = 25 MHz, fOUT = fMCLK/4096 3
Operating temperature range (Industrial B version) -40 105 °C 5
VDD to AGND -0.3 6 V TA = 25°C 5
VDD to DGND -0.3 6 V TA = 25°C 5
AGND to DGND -0.3 0.3 V TA = 25°C 5
CAP/2.5V 2.75 V TA = 25°C 5
Digital I/O voltage to DGND -0.3 V TA = 25°C; upper limit printed as VDD + 0.3 V 5
Analog I/O voltage to AGND -0.3 V TA = 25°C; upper limit printed as VDD + 0.3 V 5
Storage temperature range -65 150 °C TA = 25°C 5
Maximum junction temperature 150 °C TA = 25°C 5
Lead temperature, soldering 300 °C 10 sec 5
IR reflow peak temperature 220 °C 5
MCLK period t1 40 ns MCLK period; TMIN to TMAX 4
MCLK high duration t2 16 ns MCLK high duration; TMIN to TMAX 4
MCLK low duration t3 16 ns MCLK low duration; TMIN to TMAX 4
SCLK period t4 25 ns SCLK period; TMIN to TMAX 4
SCLK high duration t5 10 ns SCLK high duration; TMIN to TMAX 4
SCLK low duration t6 10 ns SCLK low duration; TMIN to TMAX 4
FSYNC to SCLK falling edge setup time t7 5 ns TMIN to TMAX 4
FSYNC to SCLK hold time t8 10 ns TMIN to TMAX 4
Data setup time t9 5 ns TMIN to TMAX 4
Data hold time t10 3 ns TMIN to TMAX 4
SCLK high to FSYNC falling edge setup time t11 5 ns TMIN to TMAX 4
Integral nonlinearity INL -1 1 LSB 3
Differential nonlinearity DNL -0.5 0.5 LSB 3
Resolution 10 Bits 3
Update rate 25 MSPS 3
VOUT maximum VOUT 0.65 V 3
VOUT minimum VOUT 38 mV 3
VOUT temperature coefficient 200 ppm/°C 3
Clock feedthrough -60 dBc 3
Wake-up time 1 ms 3
Input high voltage VINH VINH 1.7 V 2.3 V to 2.7 V power supply 3
Input high voltage VINH VINH 2 V 2.7 V to 3.6 V power supply 3
Input high voltage VINH VINH 2.8 V 4.5 V to 5.5 V power supply 3
Input low voltage VINL VINL 0.5 V 2.3 V to 2.7 V power supply 3
Input low voltage VINL VINL 0.7 V 2.7 V to 3.6 V power supply 3
Input low voltage VINL VINL 0.8 V 4.5 V to 5.5 V power supply 3
Input current IINH/IINL 10 μA 3
Input capacitance CIN 3 pF 3
Low power sleep mode current 0.5 mA DAC powered down, MCLK running 3
Wideband SFDR (0 to Nyquist) SFDR -60 dBc fMCLK = 25 MHz, fOUT = fMCLK/50 3
Narrow-band SFDR (±200 kHz) SFDR -78 dBc fMCLK = 25 MHz, fOUT = fMCLK/50 3
Thermal impedance junction to ambient θJA 206 °C/W MSOP package 5
Thermal impedance junction to case θJC 44 °C/W MSOP package 5

CAD (KiCad official)

  • Symbol: AD9833WBRMZ-REEL
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: ad9833wbrmz-reel-etched.step / ad9833wbrmz-reel-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9833wbrmz-reel.step / ad9833wbrmz-reel.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (21 pp, sha256 426eb7a26ea9dc0d, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF