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AD9780BCPZ

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Analog Devices Digital To Analog Converters (DACs), LFCSP-72(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad9780bcpzfactory-2.0.0extractor-text

Verified AD9780BCPZ

by Ray · last 30 Oct 2026 · 1 record · files match
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Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 73 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD9780BCPZ · LFCSP-72(10x10) · 73 pins
  • ✓copper: 73 copper pads, none touching another net
  • ✓datasheet: all 73 pin names found in the 32-page datasheet
  • ✓distributor: lcsc C653861, digikey AD9780BCPZ-ND, mouser 584-AD9780BCPZ
  • ✓family: QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-nte6bnx5/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.31)
  • ✓pads: 73 pins = 73 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 73 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad9780bcpz.kicad_sym✓ ad9780bcpz.kicad_mod✓ ad9780bcpz.step
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AD9780BCPZ

Analog Devices · Digital To Analog Converters (DACs) · LFCSP-72(10x10)

AD9780BCPZ from Analog Devices, in a LFCSP-72(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CVDD18 power_in Clock supply voltage, 1.8 V nominal.
2 CVSS power_in Clock supply return.
3 CLKP input Positive leg of the differential DAC sampling clock input.
4 CLKN input Negative leg of the differential DAC sampling clock input.
5 CVSS power_in Clock supply return.
6 CVDD18 power_in Clock supply voltage, 1.8 V nominal.
7 DVSS power_in Digital common (ground).
8 DVDD18 power_in Digital supply voltage, 1.8 V nominal.
9 D11P input Positive leg of LVDS data input bit D11 (MSB).
10 D11N input Negative leg of LVDS data input bit D11 (MSB).
11 D10P input Positive leg of LVDS data input bit D10.
12 D10N input Negative leg of LVDS data input bit D10.
13 D9P input Positive leg of LVDS data input bit D9.
14 D9N input Negative leg of LVDS data input bit D9.
15 D8P input Positive leg of LVDS data input bit D8.
16 D8N input Negative leg of LVDS data input bit D8.
17 D7P input Positive leg of LVDS data input bit D7.
18 D7N input Negative leg of LVDS data input bit D7.
19 D6P input Positive leg of LVDS data input bit D6.
20 D6N input Negative leg of LVDS data input bit D6.
21 D5P input Positive leg of LVDS data input bit D5.
22 D5N input Negative leg of LVDS data input bit D5.
23 D4P input Positive leg of LVDS data input bit D4.
24 D4N input Negative leg of LVDS data input bit D4.
25 DCOP output Positive leg of the differential data clock output, clocked at the DAC sample rate.
26 DCON output Negative leg of the differential data clock output, clocked at the DAC sample rate.
27 DVDD33 power_in Digital input and output pad ring supply voltage, 3.3 V.
28 DVSS power_in Digital common (ground).
29 DCIP input Positive leg of the differential data clock input, aligned with the input data.
30 DCIN input Negative leg of the differential data clock input, aligned with the input data.
31 D3P input Positive leg of LVDS data input bit D3.
32 D3N input Negative leg of LVDS data input bit D3.
33 D2P input Positive leg of LVDS data input bit D2.
34 D2N input Negative leg of LVDS data input bit D2.
35 D1P input Positive leg of LVDS data input bit D1.
36 D1N input Negative leg of LVDS data input bit D1.
37 D0P input Positive leg of LVDS data input bit D0 (LSB).
38 D0N input Negative leg of LVDS data input bit D0 (LSB).
39 NC unconnected No connection; leave floating.
40 NC unconnected No connection; leave floating.
41 NC unconnected No connection; leave floating.
42 NC unconnected No connection; leave floating.
43 NC unconnected No connection; leave floating.
44 NC unconnected No connection; leave floating.
45 NC unconnected No connection; leave floating.
46 NC unconnected No connection; leave floating.
47 DVDD18 power_in Digital supply voltage, 1.8 V nominal.
48 DVSS power_in Digital common (ground).
49 SDO output Serial port data output, used in protocols with separate transmit and receive lines.
50 SDIO bidirectional Serial port data input in 4-wire mode or bidirectional serial data line in 3-wire mode.
51 SCLK input Serial port clock input.
52 CSB input Serial port chip select, active low.
53 RESET input Chip reset, active high.
54 FS ADJ passive Full-scale current output adjust.
55 REFIO bidirectional Analog reference input/output, 1.2 V nominal.
56 AVDD33 power_in Analog supply voltage, 3.3 V.
57 AVDD33 power_in Analog supply voltage, 3.3 V.
58 AVSS power_in Analog common (ground).
59 IOUT2P output DAC channel 2 current output; full-scale current is sourced when all data bits are 1s.
60 IOUT2N output Complementary DAC channel 2 current output; full-scale current is sourced when all data bits are 0s.
61 AVSS power_in Analog common (ground).
62 AUX2P output Positive leg of the differential auxiliary DAC channel 2 current output.
63 AUX2N output Negative leg of the differential auxiliary DAC channel 2 current output.
64 AVSS power_in Analog common (ground).
65 AUX1N output Negative leg of the differential auxiliary DAC channel 1 current output.
66 AUX1P output Positive leg of the differential auxiliary DAC channel 1 current output.
67 AVSS power_in Analog common (ground).
68 IOUT1N output Complementary DAC channel 1 current output; full-scale current is sourced when all data bits are 0s.
69 IOUT1P output DAC channel 1 current output; full-scale current is sourced when all data bits are 1s.
70 AVSS power_in Analog common (ground).
71 AVDD33 power_in Analog supply voltage, 3.3 V.
72 AVDD33 power_in Analog supply voltage, 3.3 V.
73 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-72(10x10)
Category ADC/DAC/Data Conversion
Pins 73

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Offset Error -0.001 0 0.001 % FSR 3
Gain Error (with Internal Reference) -2 2 % FSR with internal reference 3
Full-Scale Output Current 8.66 20.2 31.66 mA Based on a 10 kΩ external resistor 3
Output Compliance Range (main DAC) -1 1 V 3
Full-Scale Output Current (AUX DAC) -2 2 mA 3
Output Compliance Range (Source, AUX DAC) 0 1.6 V 3
Output Compliance Range (Sink, AUX DAC) 0.8 1.6 V 3
Analog Supply Voltage AVDD33 AVDD33 3.13 3.3 3.47 V 3
Clock Supply Voltage CVDD18 CVDD18 1.7 1.8 1.9 V 3
Digital Supply Voltage DVDD33 DVDD33 3.13 3.3 3.47 V 3
Digital Supply Voltage DVDD18 DVDD18 1.7 1.8 1.9 V 3
Power-Down Mode 3 5 mW 3
Supply Current AVDD33 AVDD33 55 58 mA fDAC = 500 MSPS, fOUT = 20 MHz 3
Supply Current CVDD18 CVDD18 34 38 mA fDAC = 500 MSPS, fOUT = 20 MHz 3
Supply Current DVDD33 DVDD33 13 15 mA fDAC = 500 MSPS, fOUT = 20 MHz 3
Supply Current DVDD18 DVDD18 68 85 mA fDAC = 500 MSPS, fOUT = 20 MHz 3
Supply voltage AVDD33, DVDD33 AVDD33, DVDD33 -0.3 3.6 V with respect to AGND, DGND, CGND 6
Supply voltage DVDD18, CVDD18 DVDD18, CVDD18 -0.3 1.98 V with respect to AGND, DGND, CGND 6
AGND voltage AGND -0.3 0.3 V with respect to DGND, CGND 6
DGND voltage DGND -0.3 0.3 V with respect to AGND, CGND 6
CGND voltage CGND -0.3 0.3 V with respect to AGND, DGND 6
REFIO voltage REFIO -0.3 V with respect to AGND; printed upper limit AVDD33 + 0.3 V 6
Current/AUX output voltage IOUT1P, IOUT1N, IOUT2P, IOUT2N, AUX1P, AUX1N, AUX2P, AUX2N -1 V with respect to AGND; printed upper limit AVDD33 + 0.3 V 6
Data input voltage D15 to D0 D15 to D0 -0.3 V with respect to DGND; printed upper limit DVDD33 + 0.3 V 6
Clock input voltage CLKP, CLKN CLKP, CLKN -0.3 V with respect to CGND; printed upper limit CVDD18 + 0.3 V 6
Serial port voltage CSB, SCLK, SDIO, SDO CSB, SCLK, SDIO, SDO -0.3 V with respect to DGND; printed upper limit DVDD33 + 0.3 V 6
Junction Temperature TJ 125 °C 6
Storage Temperature TSTG -65 150 °C 6
Thermal Resistance junction-to-ambient θJA 25 °C/W JEDEC 4-layer board, no airflow; CP-72-1 exposed pad soldered to PCB 6

CAD (KiCad official)

  • Symbol: AD9780BCPZ
  • Footprint: Package_DFN_QFN:QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-72(10x10), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: ad9780bcpz-etched.step / ad9780bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9780bcpz.step / ad9780bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (32 pp, sha256 b039d7a4cf31fe71, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF