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AD9746BCPZ

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Analog Devices Digital To Analog Converters (DACs), LFCSP-72(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad9746bcpzfactory-2.0.0extractor-text

Verified AD9746BCPZ

by Ray · last 31 Oct 2026 · 1 record · files match
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Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 73 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD9746BCPZ · LFCSP-72(10x10) · 73 pins
  • ✓copper: 73 copper pads, none touching another net
  • ✓datasheet: all 73 pin names found in the 28-page datasheet
  • ✓distributor: lcsc C653771, digikey 505-AD9746BCPZ-ND, mouser 584-AD9746BCPZ
  • ✓family: QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-34wxuice/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.27)
  • ✓pads: 73 pins = 73 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 73 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad9746bcpz.kicad_sym✓ ad9746bcpz.kicad_mod✓ ad9746bcpz.step
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AD9746BCPZ

Analog Devices · Digital To Analog Converters (DACs) · LFCSP-72(10x10)

AD9746BCPZ from Analog Devices, in a LFCSP-72(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CVDD18 power_in Clock supply voltage (1.8 V).
2 CVSS power_in Clock supply common (0 V).
3 CLKP input Differential DAC clock input.
4 CLKN input Complementary differential DAC clock input.
5 CVSS power_in Clock supply common (0 V).
6 CVDD18 power_in Clock supply voltage (1.8 V).
7 DVSS power_in Digital supply common (0 V).
8 DVDD18 power_in Digital core supply voltage (1.8 V).
9 P1D13 input Port 1 data bit 13 input.
10 P1D12 input Port 1 data bit 12 input.
11 P1D11 input Port 1 data bit 11 input.
12 P1D10 input Port 1 data bit 10 input.
13 P1D9 input Port 1 data bit 9 input.
14 P1D8 input Port 1 data bit 8 input.
15 P1D7 input Port 1 data bit 7 input.
16 P1D6 input Port 1 data bit 6 input.
17 P1D5 input Port 1 data bit 5 input.
18 P1D4 input Port 1 data bit 4 input.
19 P1D3 input Port 1 data bit 3 input.
20 P1D2 input Port 1 data bit 2 input.
21 P1D1 input Port 1 data bit 1 input.
22 P1D0 input Port 1 data bit 0 input.
23 NC unconnected No connect.
24 NC unconnected No connect.
25 DCO output Data clock output; use to clock the data source.
26 NC unconnected No connect.
27 DVDD33 power_in Digital I/O supply voltage (3.3 V).
28 DVSS power_in Digital supply common (0 V).
29 IQSEL input I/Q framing signal for single-port mode operation.
30 NC unconnected No connect.
31 P2D13 input Port 2 data bit 13 input.
32 P2D12 input Port 2 data bit 12 input.
33 P2D11 input Port 2 data bit 11 input.
34 P2D10 input Port 2 data bit 10 input.
35 P2D9 input Port 2 data bit 9 input.
36 P2D8 input Port 2 data bit 8 input.
37 P2D7 input Port 2 data bit 7 input.
38 P2D6 input Port 2 data bit 6 input.
39 P2D5 input Port 2 data bit 5 input.
40 P2D4 input Port 2 data bit 4 input.
41 P2D3 input Port 2 data bit 3 input.
42 P2D2 input Port 2 data bit 2 input.
43 P2D1 input Port 2 data bit 1 input.
44 P2D0 input Port 2 data bit 0 input.
45 NC unconnected No connect.
46 NC unconnected No connect.
47 DVDD18 power_in Digital core supply voltage (1.8 V).
48 DVSS power_in Digital supply common (0 V).
49 SDO output Serial peripheral interface data output.
50 SDIO bidirectional Serial peripheral interface data input and optional data output.
51 SCLK input Serial peripheral interface clock input.
52 CSB input Serial peripheral interface chip select input, active low.
53 RESET input Hardware reset, active high.
54 FSADJ passive Full-scale current output adjust; connect a 10 kΩ resistor to AVSS.
55 REFIO bidirectional Reference input/output; connect a 0.1 μF capacitor to AVSS.
56 AVDD33 power_in Analog supply voltage (3.3 V).
57 AVDD33 power_in Analog supply voltage (3.3 V).
58 AVSS power_in Analog supply common (0 V).
59 IOUT2P output DAC2 current output true; sources full-scale current when input data bits are all 1.
60 IOUT2N output DAC2 current output complement; sources full-scale current when data bits are all 0.
61 AVSS power_in Analog supply common (0 V).
62 AUX2P output Auxiliary DAC2 default current output pin.
63 AUX2N output Auxiliary DAC2 optional output pin; enable through SPI.
64 AVSS power_in Analog supply common (0 V).
65 AUX1N output Auxiliary DAC1 optional output pin; enable through SPI.
66 AUX1P output Auxiliary DAC1 default current output pin.
67 AVSS power_in Analog supply common (0 V).
68 IOUT1N output Complementary DAC1 current output; sources full-scale current when data bits are all 0.
69 IOUT1P output DAC1 current output; sources full-scale current when data bits are all 1.
70 AVSS power_in Analog supply common (0 V).
71 AVDD33 power_in Analog supply voltage (3.3 V).
72 AVDD33 power_in Analog supply voltage (3.3 V).
73 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-72(10x10)
Category ADC/DAC/Data Conversion
Pins 73

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Full-Scale Output Current IFS 8.6 31.7 mA Main DAC outputs 4
Output Compliance Voltage -1 1 V Main DAC outputs 4
Aux DAC Full-Scale Output Current -2 2 mA Auxiliary DAC outputs 4
Aux DAC Compliance Voltage Range, Sink Current 0.8 1.6 V Auxiliary DAC outputs 4
Aux DAC Compliance Voltage Range, Source Current 0 1.6 V Auxiliary DAC outputs 4
Reference External Input Voltage Range 1.15 1.3 V Reference input/output 4
Supply Voltage AVDD33, DVDD33 AVDD33, DVDD33 3.13 3.47 V 4
Supply Voltage CVDD18, DVDD18 CVDD18, DVDD18 1.7 1.9 V 4
Operating Temperature -40 85 °C 4
AVDD33 Supply Current IAVDD33 56 60 mA IFS = 20 mA, full-scale digital input, maximum sample rate 4
DVDD33 Supply Current IDVDD33 12 16 mA IFS = 20 mA, full-scale digital input, maximum sample rate 4
CVDD18 Supply Current ICVDD18 18 22 mA IFS = 20 mA, full-scale digital input, maximum sample rate 4
DVDD18 Supply Current IDVDD18 31 35 mA IFS = 20 mA, full-scale digital input, maximum sample rate 4
Power Dissipation 310 355 mW fDAC = 250 MSPS, fOUT = 20 MHz 4
Power Dissipation, DAC Outputs Disabled 125 mW DAC Outputs Disabled 4
Power Dissipation, Full Device Power-Down 3 mW Full Device Power-Down 4
Resolution 14 Bits 4
Differential Nonlinearity DNL 0.5 LSB printed ±0.5 4
Integral Nonlinearity INL 1 LSB printed ±1.0 4
Offset Error 0.001 %FSR printed ±0.001 4
Offset Error Temperature Coefficient 0.1 ppm/°C 4
Gain Error 2 %FSR printed ±2.0 4
Gain Error Temperature Coefficient 100 ppm/°C 4
Gain Matching (DAC1 to DAC2) 1 %FSR printed ±1.0 4
Output Resistance 10 MΩ Main DAC outputs 4
Aux DAC Resolution 10 Bits 4
Aux DAC Output Resistance 1 MΩ 4
Aux DAC Monotonicity 10 Bits 4
Reference Output Voltage 1.2 V 4
Reference Output Voltage Temperature Coefficient 10 ppm/°C 4
Reference Input or Output Resistance 5 kΩ 4
Clock Differential Peak-to-Peak Voltage 400 800 1600 mV CLKP, CLKN 7
Clock Common-Mode Voltage 300 400 500 mV CLKP, CLKN 7
Clock Input Frequency 250 MHz CLKP, CLKN 7
DCO Output Voltage High 2.4 V Data clock output 7
DCO Output Voltage Low 0.4 V Data clock output 7
DAC Clock to Data Clock Output Delay tDCO 2 2.2 2.8 ns 7
Data Port Input Voltage High 2 V Data port inputs 7
Data Port Input Voltage Low 0.8 V Data port inputs 7
Data to DAC Clock Setup Time tDBS 400 ps Dual-Port Mode 7
Data to DAC Clock Hold Time tDBH 1200 ps Dual-Port Mode 7
SCLK Frequency fSCLK 40 MHz 7
SCLK Pulse Width High tPWH 10 ns 7
SCLK Pulse Width Low tPWL 10 ns 7
RESET Pulse Width High 10 ns 7
Wake-Up Time From DAC Outputs Disabled 200 μs 7
Wake-Up Time From Full Device Power-Down 1200 μs 7
AVDD33, DVDD33 Supply Voltage -0.3 3.6 V With respect to AVSS, DVSS, CVSS 8
DVDD18, CVDD18 Supply Voltage -0.3 1.98 V With respect to AVSS, DVSS, CVSS 8
AVSS, DVSS, CVSS Mutual Voltage -0.3 0.3 V Each with respect to the other two 8
IOUTxP/N, AUXxP/N Voltage -1 V With respect to AVSS; upper limit AVDD33 + 0.3 V 8
REFIO Voltage -0.3 V With respect to AVSS; upper limit AVDD33 + 0.3 V 8
P1D, P2D, RESET, CSB, SCLK, SDIO, SDO Voltage -0.3 V With respect to DVSS; upper limit DVDD33 + 0.3 V 8
CLKP, CLKN Voltage -0.3 V With respect to CVSS; upper limit CVDD18 + 0.3 V 8
Junction Temperature TJ 125 °C 8
Storage Temperature -65 150 °C 8
Thermal Resistance Junction to Ambient θJA 25 °C/W CP-72-1, exposed pad soldered to PCB, JEDEC 4-layer board, no airflow 8

CAD (KiCad official)

  • Symbol: AD9746BCPZ
  • Footprint: Package_DFN_QFN:QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-72(10x10), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: ad9746bcpz-etched.step / ad9746bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9746bcpz.step / ad9746bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 8681e01648dc481c, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF