component
AD9574BCPZ
Public Made by Adomby adom
Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482
{
"slug": "ad9574bcpz",
"version": "0.1.0",
"type": "component",
"description": "Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"rtc-clock chip",
"ad9574bcpz",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"ad9574bcpz.kicad_sym",
"ad9574bcpz.kicad_mod",
"ad9574bcpz.glb",
"ad9574bcpz.step",
"ad9574bcpz.lbr",
"docs/hero.png",
"docs/ad9574bcpz-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"ad9574bcpz-hero.glb",
"ad9574bcpz-hero.overlay.json",
"ad9574bcpz-etched.glb"
],
"component": {
"mpn": "AD9574BCPZ",
"manufacturer": "Analog Devices",
"package": "LFCSP-48(7x7)",
"pin_count": 49,
"category": "RTC/Clock Chip",
"subcategory": "Clock Generators / Frequency Synthesizers / PLL",
"datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9574.pdf",
"parts": {
"symbol": "ad9574bcpz.kicad_sym",
"footprint": "ad9574bcpz.kicad_mod",
"model_3d": "ad9574bcpz-hero.glb",
"model_3d_plain": "ad9574bcpz-etched.glb",
"model_3d_step": "ad9574bcpz-etched.step",
"model_3d_step_plain": "ad9574bcpz.step",
"lbr": "ad9574bcpz.lbr"
},
"distributor_links": {
"lcsc": "C653596",
"digikey": "505-AD9574BCPZ-ND",
"mouser": "584-AD9574BCPZ"
},
"distributor_check": {
"checked_at": "2026-10-30T20:53:07Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "505-AD9574BCPZ-ND",
"status": "found"
},
"mouser": {
"pn": "584-AD9574BCPZ",
"status": "found",
"lifecycle": "Restricted Availability"
}
},
"pins": [
{
"number": "1",
"name": "REF0_P",
"type": "input",
"description": "Reference Clock Input 0, Positive, configurable via PPR0 (Pin 47)."
},
{
"number": "2",
"name": "REF0_N",
"type": "input",
"description": "Reference Clock Input 0, Negative, configurable via PPR0 (Pin 47)."
},
{
"number": "3",
"name": "VDD_REF0",
"type": "power_in",
"description": "3.3 V input supply for Reference Clock Input 0 (REF0_x), supplying the single-ended input receiver and internal LDO regulator for the differential receiver."
},
{
"number": "4",
"name": "VDD_REF1",
"type": "power_in",
"description": "3.3 V input supply for Reference Clock Input 1 (REF1_x), supplying the single-ended input receiver and internal LDO regulator for the differential receiver."
},
{
"number": "5",
"name": "REF1_N",
"type": "input",
"description": "Reference Clock Input 1, Negative, configurable via PPR0 (Pin 47)."
},
{
"number": "6",
"name": "REF1_P",
"type": "input",
"description": "Reference Clock Input 1, Positive, configurable via PPR0 (Pin 47)."
},
{
"number": "7",
"name": "PPR2",
"type": "input",
"description": "Pin Program Reader 2; connect a resistor to this pin to configure the OUT0 and OUT1 channels."
},
{
"number": "8",
"name": "VDD_OUT01",
"type": "power_in",
"description": "3.3 V input for the CMOS drivers of OUT0_x and OUT1_x and source for an internal 1.8 V LDO regulator for their differential drivers."
},
{
"number": "9",
"name": "OUT0_N",
"type": "output",
"description": "Clock Output 0, Negative, configurable via PPR2 (Pin 7)."
},
{
"number": "10",
"name": "OUT0_P",
"type": "output",
"description": "Clock Output 0, Positive, configurable via PPR2 (Pin 7)."
},
{
"number": "11",
"name": "OUT1_P",
"type": "output",
"description": "Clock Output 1, Positive, configurable via PPR2 (Pin 7)."
},
{
"number": "12",
"name": "OUT1_N",
"type": "output",
"description": "Clock Output 1, Negative, configurable via PPR2 (Pin 7)."
},
{
"number": "13",
"name": "VDD_PLL",
"type": "power_in",
"description": "3.3 V input to the internal LDO regulator for the PLL."
},
{
"number": "14",
"name": "LD",
"type": "output",
"description": "3.3 V CMOS PLL lock detector status; Logic 0 = unlocked, Logic 1 = locked."
},
{
"number": "15",
"name": "LF",
"type": "passive",
"description": "Analog loop filter; connect a capacitor or series RC network from this pin to LDO_BYP (Pin 16)."
},
{
"number": "16",
"name": "LDO_BYP",
"type": "passive",
"description": "Analog LDO bypass; connect a 470 nF capacitor from this pin to GND."
},
{
"number": "17",
"name": "VDD_VCO",
"type": "power_in",
"description": "3.3 V input to the internal LDO regulator for the VCO."
},
{
"number": "18",
"name": "VDD_RFDIV",
"type": "power_in",
"description": "3.3 V input to the internal LDO regulator for the VCO RF dividers."
},
{
"number": "19",
"name": "PPR6",
"type": "input",
"description": "Pin Program Reader 6; connect a resistor to this pin to configure the MCLK_x input."
},
{
"number": "20",
"name": "RESET",
"type": "input",
"description": "3.3 V CMOS reset; Logic 0 (GND) initializes the device to its default state, with an internal 30 kΩ pull-up resistor."
},
{
"number": "21",
"name": "OUT6_N",
"type": "output",
"description": "Clock Output 6, Negative, configurable via PPR4 (Pin 26)."
},
{
"number": "22",
"name": "OUT6_P",
"type": "output",
"description": "Clock Output 6, Positive, configurable via PPR4 (Pin 26)."
},
{
"number": "23",
"name": "VDD_OUT6",
"type": "power_in",
"description": "3.3 V input for the CMOS drivers of OUT6_x and source for an internal 1.8 V LDO regulator for the 1.8 V CMOS and differential drivers of OUT6_x."
},
{
"number": "24",
"name": "PPR5",
"type": "input",
"description": "Pin Program Reader 5; connect a resistor to this pin to configure the reference clock frequency error threshold."
},
{
"number": "25",
"name": "REFMON",
"type": "input",
"description": "Reference frequency monitor enable/disable; do not float or toggle during operation, connect to a static Logic 0 or Logic 1."
},
{
"number": "26",
"name": "PPR4",
"type": "input",
"description": "Pin Program Reader 4; connect a resistor to this pin to configure the OUT6 channel."
},
{
"number": "27",
"name": "PPR3",
"type": "input",
"description": "Pin Program Reader 3; connect a resistor to this pin to configure the OUT4 and OUT5 channels."
},
{
"number": "28",
"name": "OUT4_N",
"type": "output",
"description": "Clock Output 4, Negative, configurable via PPR3 (Pin 27)."
},
{
"number": "29",
"name": "OUT4_P",
"type": "output",
"description": "Clock Output 4, Positive, configurable via PPR3 (Pin 27)."
},
{
"number": "30",
"name": "VDD_OUT4",
"type": "power_in",
"description": "3.3 V input for an internal 1.8 V LDO regulator for the differential drivers of OUT4_x."
},
{
"number": "31",
"name": "VDD_OUT5",
"type": "power_in",
"description": "3.3 V input for an internal 1.8 V LDO regulator for the differential drivers of OUT5_x."
},
{
"number": "32",
"name": "OUT5_P",
"type": "output",
"description": "Clock Output 5, Positive, configurable via PPR3 (Pin 27)."
},
{
"number": "33",
"name": "OUT5_N",
"type": "output",
"description": "Clock Output 5, Negative, configurable via PPR3 (Pin 27)."
},
{
"number": "34",
"name": "REF_FLO",
"type": "output",
"description": "3.3 V CMOS low reference frequency status; Logic 1 indicates reference below the lower threshold, open-drain with internal 30 kΩ pull-down."
},
{
"number": "35",
"name": "REF_FHI",
"type": "output",
"description": "3.3 V CMOS high reference frequency status; Logic 1 indicates reference above the upper threshold, open-drain with internal 30 kΩ pull-down."
},
{
"number": "36",
"name": "VDD_OUT23",
"type": "power_in",
"description": "3.3 V input for an internal 1.8 V LDO regulator for the differential drivers of OUT2_x and OUT3_x."
},
{
"number": "37",
"name": "OUT2_N",
"type": "output",
"description": "Clock Output 2, Negative (HSTL)."
},
{
"number": "38",
"name": "OUT2_P",
"type": "output",
"description": "Clock Output 2, Positive (HSTL)."
},
{
"number": "39",
"name": "OUT3_P",
"type": "output",
"description": "Clock Output 3, Positive (HSTL)."
},
{
"number": "40",
"name": "OUT3_N",
"type": "output",
"description": "Clock Output 3, Negative (HSTL)."
},
{
"number": "41",
"name": "PPR1",
"type": "input",
"description": "Pin Program Reader 1; connect a resistor to this pin to select a predefined frequency translation configuration."
},
{
"number": "42",
"name": "VDD_MCLK",
"type": "power_in",
"description": "3.3 V input for Reference Monitor Clock (MCLK_x), supplying the single-ended input receiver and internal LDO regulator for the differential receiver."
},
{
"number": "43",
"name": "REF_SW",
"type": "output",
"description": "3.3 V CMOS reference switchover status indicator showing when the device is switching references."
},
{
"number": "44",
"name": "REF_ACT",
"type": "output",
"description": "3.3 V CMOS reference active status indicator showing whether REF0 or REF1 is the active reference."
},
{
"number": "45",
"name": "MCLK_P",
"type": "input",
"description": "Reference monitor clock normal input, configurable via PPR6."
},
{
"number": "46",
"name": "MCLK_N",
"type": "input",
"description": "Reference monitor clock complementary input, configurable via PPR6."
},
{
"number": "47",
"name": "PPR0",
"type": "input",
"description": "Pin Program Reader 0; connect a resistor to this pin to configure the reference clock inputs."
},
{
"number": "48",
"name": "REF_SEL",
"type": "input",
"description": "3.3 V CMOS reference clock select (Logic 0 = REF0, Logic 1 = REF1), with internal 30 kΩ pull-down."
},
{
"number": "49",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-sonnet-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Datasheet text says MCLK_x is configurable via PPR6 (Pin 18), but PPR6 is Pin 19 per Table 18 and Ta; Table 18 says OUT2/OUT3 are configurable via PPR2 (Pin 7), but they are HSTL outputs whose frequency; Pin types for LF (Input/Output analog) and LDO_BYP (Output analog) chosen as passive; Figure 4 label"
],
"pages_sent": 13,
"cost_usd": 0.216,
"at": "2026-10-30T20:52:57"
},
"datasheet": {
"url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9574.pdf",
"pages": 35,
"sha256": "d2a8390399782645",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 49,
"described": 49,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "ad9574bcpz.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
7.0,
7.0,
0.77
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",
"checked": "2026-10-30",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ad9574bcpz-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
7.0,
7.0,
0.77
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "7f00fee18fcc8e1f03b1399af91002793d1496ddee76d2e6d140b311e6e6b7bd",
"checked": "2026-10-30",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
],
"package_dims": {
"package_code": "CP-48-5",
"source_page": 35,
"D": {
"nom_mm": 7.0,
"range_mm": [
6.9,
7.1
]
},
"E1": {
"nom_mm": 7.0,
"range_mm": [
6.9,
7.1
]
},
"e": {
"nom_mm": 0.5,
"range_mm": [
null,
null
]
},
"A": {
"nom_mm": 0.75,
"range_mm": [
0.7,
0.8
]
},
"source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
"model_check": {
"file": "ad9574bcpz.step",
"verdict": "PASS",
"reasons": [
"height within the datasheet's package drawing"
],
"by": "factory/package_fit.py"
}
}
}
}