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AD9544BCPZ

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Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipad9544bcpzfactory-2.0.0extractor-text

Verified AD9544BCPZ

by Ray · last 30 Oct 2026 · 1 record · files match
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Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD9544BCPZ · LFCSP-48(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 62-page datasheet
  • ✓distributor: lcsc C653560, digikey 505-AD9544BCPZ-ND, mouser 584-AD9544BCPZ
  • ✓family: QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-f3_2zmuh/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.62)
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad9544bcpz.kicad_sym✓ ad9544bcpz.kicad_mod✓ ad9544bcpz.step
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Ray Publish 0.1.0 3ecc421 3d ago

AD9544BCPZ

Analog Devices · Clock Generators / Frequency Synthesizers / PLL · LFCSP-48(7x7)

AD9544BCPZ from Analog Devices, in a LFCSP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SDO/M5 output Serial data output (SDO) for reading data in 4-wire SPI mode; when not in 4-wire SPI mode it is configurable status/control pin M5, and its VOH and VIH track the VDDIOA supply.
2 SCLK/SCL input Serial clock input in SPI mode (SCLK) or I²C mode (SCL); its VIH and VOH follow the VDDIOA supply voltage.
3 VDDIOA power_in Serial port power supply, valid at 1.8 V, 2.5 V, or 3.3 V; it can be connected to the VDD bus for 1.8 V operation.
4 SDIO/SDA bidirectional Serial data input/output in SPI mode (SDIO) or serial data line in I²C mode (SDA); it has no internal pull-up or pull-down and its VIH and VOH follow VDDIOA.
5 CSB/M6 bidirectional Active-low chip select in SPI mode (CSB) with an internal 10 kΩ pull-up; configurable status/control pin M6 when not in SPI mode, with VIH and VOH following VDDIOA.
6 VDD power_in 1.8 V power supply pin.
7 LDO0 input APLL0 loop filter voltage regulator bypass; connect a 0.22 µF capacitor from this pin to ground, which is the AC ground reference for the APLL0 loop filter.
8 LF0 bidirectional APLL0 loop filter node; connect a 3.9 nF capacitor from this pin to pin 7 (LDO0).
9 VDD power_in 1.8 V power supply pin.
10 VDD power_in 1.8 V power supply pin.
11 OUT0AP output PLL0 output 0A (true), configurable as HCSL, LVDS, CML, or CMOS.
12 OUT0AN output PLL0 complementary output 0A, configurable as HCSL, LVDS, CML, or CMOS.
13 VDD power_in 1.8 V power supply pin.
14 OUT0BP output PLL0 output 0B (true), configurable as HCSL, LVDS, CML, or CMOS.
15 OUT0BN output PLL0 complementary output 0B, configurable as HCSL, LVDS, CML, or CMOS.
16 DNC unconnected Do not connect; leave floating.
17 OUT0CP output PLL0 output 0C (true), configurable as HCSL, LVDS, CML, or CMOS.
18 OUT0CN output PLL0 complementary output 0C, configurable as HCSL, LVDS, CML, or CMOS.
19 VDD power_in 1.8 V power supply pin.
20 VDD power_in 1.8 V power supply pin.
21 DNC unconnected Do not connect; leave floating.
22 OUT1BP output PLL1 output 1B (true), configurable as HCSL, LVDS, CML, or CMOS.
23 OUT1BN output PLL1 complementary output 1B, configurable as HCSL, LVDS, CML, or CMOS.
24 VDD power_in 1.8 V power supply pin.
25 OUT1AP output PLL1 output 1A (true), configurable as HCSL, LVDS, CML, or CMOS.
26 OUT1AN output PLL1 complementary output 1A, configurable as HCSL, LVDS, CML, or CMOS.
27 VDD power_in 1.8 V power supply pin.
28 VDD power_in 1.8 V power supply pin.
29 LF1 bidirectional APLL1 loop filter node; connect a 3.9 nF capacitor from this pin to pin 30 (LDO1).
30 LDO1 input APLL1 loop filter voltage regulator bypass; connect a 0.1 µF capacitor from this pin to ground, which is the AC ground reference for the APLL1 loop filter.
31 VDD power_in 1.8 V power supply pin.
32 M0 bidirectional Configurable CMOS status/control pin; its VIH and VOH follow VDDIOB and it has no internal resistor.
33 M1 bidirectional Configurable CMOS status/control pin; its VIH and VOH follow VDDIOB and it has no internal resistor.
34 VDDIOB power_in Mx pin power supply for M0 to M4, valid at 1.8 V, 2.5 V, or 3.3 V; it can be connected to the VDD bus for 1.8 V operation.
35 M2 bidirectional Configurable CMOS status/control pin; its VIH and VOH follow VDDIOB and it has no internal resistor.
36 M3 bidirectional Configurable CMOS status/control pin with an internal 100 kΩ pull-down resistor; its VIH and VOH follow VDDIOB.
37 M4 bidirectional Configurable CMOS status/control pin with an internal 100 kΩ pull-down resistor; at start-up a logic 0 selects SPI mode (default) and a logic 1 selects I²C mode.
38 REFB input Reference B input, internally biased and typically AC-coupled, accepting a differential signal with single-ended swing up to VDD; if DC-coupled it can be LVDS or 1.8 V CMOS.
39 REFBB input Complementary REFB input when REFB is differential; no connection is needed if REFB is single-ended and REFBB is unused.
40 VDD power_in 1.8 V power supply pin.
41 VDD power_in 1.8 V power supply pin.
42 XOA input System clock input, internally DC-biased and AC-coupled with a 0.01 µF capacitor unless a crystal is connected across XOA and XOB; single-ended CMOS input is possible but may cause spurs if the duty cycle is not 50%.
43 XOB input Complementary system clock input, internally DC-biased and AC-coupled with a 0.1 µF capacitor unless a crystal is connected across XOA and XOB.
44 DNC unconnected Do not connect; leave floating.
45 VDD power_in 1.8 V power supply pin.
46 REFAA input Complementary REFA input when REFA is differential; if REFA is single-ended and REFAA is unused no connection is needed, and if DC-coupled the input is 1.8 V CMOS.
47 REFA input Reference A input, internally biased and typically AC-coupled, accepting a differential signal with single-ended swing up to VDD; if DC-coupled it can be LVDS or 1.8 V CMOS.
48 RESETB input Active-low chip reset with an internal 100 kΩ pull-up; asserting it puts the chip into reset, and its VIH follows VDDIOA.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-48(7x7)
Category RTC/Clock Chip
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Slew rate for sinusoidal input 20 V/µs Minimum input slew rate for device operation; jitter degradation may occur for slew rates < 35 V/µs 7
Differential input amplitude (fIN < 500 MHz) 350 2100 mV p-p fIN < 500 MHz; instantaneous voltage on either pin must not exceed 1.3 V 7
Differential input amplitude (fIN = 500 to 750 MHz) 500 2100 mV p-p fIN = 500 MHz to 750 MHz 7
DC-coupled LVDS-compatible mode common-mode input voltage 1.125 1.375 V Applies for dc coupling to an LVDS source 7
DC-coupled LVDS-compatible mode differential input amplitude 400 1200 mV p-p Differential voltage across pins required to ensure switching between logic levels 7
Input amplitude (single-ended, AC-coupled mode) 360 1200 mV p-p Peak-to-peak single-ended swing; instantaneous voltage must not exceed 1.3 V 7
Validation timer 0.001 1048 sec Programmable in 1 ms increments 8
Excess jitter alarm threshold 1 65535 ns Programmable in 1 ns increments 8
Phase slew limiter 0.001 250 µs/sec See AN-1420 Application Note 8
HCSL differential output voltage swing (7.5 mA) 312 368 402 mV Output current 7.5 mA; terminated per Figure 32 9
CML differential output voltage swing (7.5 mA) 257 348 408 mV Output current 7.5 mA; terminated to VDD (1.8 V) per Figure 33 9
HCSL differential output voltage swing (15 mA) 631 745 809 mV Output current 15 mA; terminated per Figure 32 9
CML differential output voltage swing (15 mA) 578 729 818 mV Output current 15 mA; terminated to VDD (1.8 V) per Figure 33 9
HCSL common-mode output voltage (7.5 mA) 155 184 201 mV Output current 7.5 mA; terminated per Figure 32 9
HCSL common-mode output voltage (15 mA) 316 372 405 mV Output current 15 mA; terminated per Figure 32 9
HCSL single-ended voltage swing peak-to-peak (12 mA) 509 584 634 mV Output current 12 mA; each output terminated per Figure 37 with RL = 50 Ω 9
CML single-ended voltage swing peak-to-peak (12 mA) 456 565 644 mV Output current 12 mA; RL = 50 Ω connected to VDD (1.8 V) 9
HCSL single-ended voltage swing midpoint (12 mA) 255 292 317 mV Output current 12 mA; each output terminated per Figure 37 with RL = 50 Ω 9
HCSL single-ended voltage swing peak-to-peak (15 mA) 645 734 796 mV Output current 15 mA; each output terminated per Figure 37 with RL = 50 Ω 9
CML single-ended voltage swing peak-to-peak (15 mA) 589 721 815 mV Output current 15 mA; RL = 50 Ω connected to VDD (1.8 V) 9
HCSL single-ended voltage swing midpoint (15 mA) 322 367 398 mV Output current 15 mA; each output terminated per Figure 37 with RL = 50 Ω 9
1.8 V Supply Voltage (VDD) VDD 2 V 19
Input/Output Supply Voltage (VDDIOA, VDDIOB) VDDIOA, VDDIOB 3.6 V 19
Input voltage range (XOA, XOB, REFA, REFAA, REFB, REFBB) -0.5 V 19
Digital input voltage range (SDO/M5, SCLK/SCL, SDIO/SDA, CSB/M6) -0.5 V 19
Digital input voltage range (M0, M1, M2, M3, M4) -0.5 V 19
Storage temperature range -65 150 °C 19
Operating temperature range -40 85 °C See Thermal Resistance section 19
Lead temperature (soldering) 300 °C Soldering 10 sec 19
Junction-to-ambient thermal resistance (still air) θJA 23.9 °C/W 0.0 m/sec airflow, JEDEC JESD51-2; package CP-48-132 19
Junction-to-ambient thermal resistance (moving air, 1.0 m/s) θJMA 19.4 °C/W 1.0 m/sec airflow, JEDEC JESD51-6 19
Junction-to-ambient thermal resistance (moving air, 2.5 m/s) θJMA 18.2 °C/W 2.5 m/sec airflow, JEDEC JESD51-6 19
Junction-to-case thermal resistance θJC 1.5 °C/W Die to heat sink, MIL-STD 883 Method 1012.1 19

CAD (KiCad official)

  • Symbol: AD9544BCPZ
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: LFCSP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ad9544bcpz-etched.step / ad9544bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9544bcpz.step / ad9544bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (62 pp, sha256 9bdbe70837679cfe, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF