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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

AD9518-0ABCPZ

Analog Devices · Clock Generators / Frequency Synthesizers / PLL · LFCSP-48(7x7)

AD9518-0ABCPZ from Analog Devices, in a LFCSP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	REFMON	output	Reference Monitor output with multiple selectable functions set by Register 0x01B; CMOS level at 3.3 V.
2	LD	output	Lock Detect output with multiple selectable functions set by Register 0x01A; CMOS level at 3.3 V.
3	VCP	power_in	Charge pump supply, which must satisfy VS ≤ VCP ≤ 5.0 V and is usually 3.3 V but should be 5 V when a 5 V external VCXO is used.
4	CP	output	Charge pump output that connects to the external loop filter.
5	STATUS	output	Status output with multiple selectable functions set by Register 0x017; CMOS level at 3.3 V.
6	REF_SEL	input	Reference select input that chooses REF1 when low and REF2 when high, with an internal 30 kΩ pull-down.
7	SYNC	input	Active-low input for manual synchronization and manual holdover, with an internal 30 kΩ pull-up.
8	LF	passive	Loop filter input connected internally to the VCO control voltage node, with 31 pF of internal capacitance to ground that may affect loop filter design at large loop bandwidths.
9	BYPASS	passive	Bypasses the LDO to ground through an external capacitor.
10	VS	power_in	3.3 V power pin.
11	CLK	input	Complement of the self-biased differential clock input for the clock distribution section; may be left floating when the internal VCO is used.
12	CLK	input	Self-biased differential clock input for the clock distribution section; may be left floating when the internal VCO is used.
13	SCLK	input	Serial control port data clock input; write data is registered on its rising edge, with an internal 30 kΩ pull-down; CMOS at 3.3 V.
14	CS	input	Serial control port chip select, active low, with an internal 30 kΩ pull-up.
15	SDO	output	Unidirectional serial data output used only in unidirectional I/O mode for reading back data.
16	SDIO	bidirectional	Serial control port bidirectional serial data input and output pin; default I/O mode.
17	RESET	input	Chip reset input, active low, with an internal 30 kΩ pull-up.
18	PD	input	Chip power-down input, active low, with an internal 30 kΩ pull-up.
19	OUT4	output	One side of the differential LVPECL output pair OUT4, which operates to 1.6 GHz.
20	OUT4	output	Complementary side of the differential LVPECL output pair OUT4, which operates to 1.6 GHz.
21	VS_LVPECL	power_in	LVPECL output power pin, supplied from 2.5 V to 3.3 V nominal.
22	OUT5	output	One side of the differential LVPECL output pair OUT5, which operates to 1.6 GHz.
23	OUT5	output	Complementary side of the differential LVPECL output pair OUT5, which operates to 1.6 GHz.
24	VS	power_in	3.3 V power pin.
25	VS	power_in	3.3 V power pin.
26	VS	power_in	3.3 V power pin.
27	GND	power_in	Ground pin; the exposed paddle on the package bottom must also be connected to ground for proper operation.
28	OUT3	output	One side of the differential LVPECL output pair OUT3, which operates to 1.6 GHz.
29	OUT3	output	Complementary side of the differential LVPECL output pair OUT3, which operates to 1.6 GHz.
30	VS_LVPECL	power_in	LVPECL output power pin, supplied from 2.5 V to 3.3 V nominal.
31	VS_LVPECL	power_in	LVPECL output power pin, supplied from 2.5 V to 3.3 V nominal.
32	OUT2	output	One side of the differential LVPECL output pair OUT2, which operates to 1.6 GHz.
33	OUT2	output	Complementary side of the differential LVPECL output pair OUT2, which operates to 1.6 GHz.
34	GND	power_in	Ground pin; the exposed paddle on the package bottom must also be connected to ground for proper operation.
35	VS	power_in	3.3 V power pin.
36	NC	unconnected	No connection.
37	VS	power_in	3.3 V power pin.
38	OUT1	output	One side of the differential LVPECL output pair OUT1, which operates to 1.6 GHz.
39	OUT1	output	Complementary side of the differential LVPECL output pair OUT1, which operates to 1.6 GHz.
40	VS_LVPECL	power_in	LVPECL output power pin, supplied from 2.5 V to 3.3 V nominal.
41	OUT0	output	One side of the differential LVPECL output pair OUT0, which operates to 1.6 GHz.
42	OUT0	output	Complementary side of the differential LVPECL output pair OUT0, which operates to 1.6 GHz.
43	VS	power_in	3.3 V power pin.
44	RSET	passive	Resistor connection that sets internal bias currents; nominal value is 4.12 kΩ.
45	VS	power_in	3.3 V power pin.
46	CPRSET	passive	Resistor connection that sets the charge pump current range; nominal value is 5.1 kΩ.
47	REFIN (REF2)	input	Complement of the self-biased differential PLL reference input; alternatively a single-ended input for REF2.
48	REFIN (REF1)	input	Self-biased differential PLL reference input; alternatively a single-ended input for REF1.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-48(7x7)
Category	RTC/Clock Chip
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VS	VS	3.135	3.3	3.465	V	3.3 V ± 5%	4
LVPECL supply voltage	VS_LVPECL	2.375			V	Nominally 2.5 V to 3.3 V ± 5%	4
Charge pump supply voltage	VCP			5.25	V	Nominally 3.3 V to 5.0 V ± 5%	4
Tuning voltage	VT	0.5			V	VCP ≤ VS when using internal VCO	4
On-chip VCO frequency range		2550		2950	MHz	See Figure 11	4
VCO gain	KVCO		50		MHz/V	See Figure 6	4
Reference input frequency (differential)		0		250	MHz	Differential mode; frequencies below about 1 MHz should be dc-coupled	4
Reference input frequency (AC-coupled single-ended)		20		250	MHz	Dual single-ended mode; slew rate > 50 V/μs	4
Reference input frequency (DC-coupled single-ended)		0		250	MHz	Dual single-ended mode; slew rate > 50 V/μs; CMOS levels	4
PFD input frequency				100	MHz	Antibacklash pulse width = 1.3 ns, 2.9 ns	4
PFD input frequency				45	MHz	Antibacklash pulse width = 6.0 ns	4
Charge pump sink/source current high value	ICP		4.8		mA	With CPRSET = 5.1 kΩ	5
Charge pump sink/source current low value	ICP		0.6		mA		5
Clock input frequency (VCO divider)		0		2.4	GHz	High frequency distribution (VCO divider)	6
Clock input frequency (VCO divider bypassed)		0		1.6	GHz	Distribution only (VCO divider bypassed)	6
Clock input common-mode voltage	VCM	1.3	1.57	1.8	V	Self-biased; enables ac coupling	6
LVPECL output differential voltage	VOD	550	790	980	mV	Default amplitude setting; driver not toggling; termination 50 Ω to VS − 2 V	6
LVPECL output frequency, maximum				2950	MHz	Using direct to output	6
LVPECL output rise time	tRP	70		180	ps	20% to 80%, measured differentially; termination 50 Ω to VS − 2 V	6
LVPECL output fall time	tFP	70		180	ps	80% to 20%, measured differentially; termination 50 Ω to VS − 2 V	6
Output skew, LVPECL outputs sharing same divider		5		15	ps	Difference between any two similar delay paths at same voltage and temperature	6
Output skew, LVPECL outputs on different dividers		13		40	ps	Difference between any two similar delay paths at same voltage and temperature	6
Power-on default power dissipation			0.76	1	W	No clock; no programming; default register values; excludes external resistors	11
Full operation power dissipation			1.1	1.7	W	PLL on; internal VCO = 2750 MHz; VCO divider = 2; all channel dividers on; six LVPECL outputs at 687.5 MHz	11
Power-down power dissipation			75	185	mW	PD pin pulled low; excludes power in terminations	11
Power-down maximum sleep power dissipation				31	mW	PD pin pulled low; PLL power-down; SYNC and REF for distribution power-down	11
Operating ambient temperature (industrial)	TA	-40		85	°C	Specified over full VS and TA range	4
Supply voltage VS to GND	VS	-0.3		3.6	V	VS, VS_LVPECL to GND	13
Charge pump supply voltage VCP to GND	VCP	-0.3		5.8	V	VCP to GND	13
REFIN to REFIN differential voltage		-3.3		3.3	V	REFIN to REFIN	13
CLK to CLK differential voltage		-1.2		1.2	V	CLK to CLK	13
Junction temperature	TJ			150	°C		13
Storage temperature range		-65		150	°C		13
Lead temperature				300	°C	10 sec	13
Thermal resistance, junction-to-ambient (48-lead LFCSP)	θJA		24.7		°C/W	4-layer board, still air, per EIA/JESD51-2	13
CPRSET pin resistor	CPRSET		5.1		kΩ	Sets internal CP current range, nominally 4.8 mA; connect to ground	4
RSET pin resistor	RSET		4.12		kΩ	Sets internal biasing currents; connect to ground	4
BYPASS pin capacitor	CBP		220		nF	Bypass for internal LDO regulator; connect to ground	4

CAD (KiCad official)

Symbol: AD9518-0ABCPZ
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: LFCSP-48(7x7) (KiCad packages3D, STEP)
3D model files: ad9518-0abcpz-etched.step / ad9518-0abcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9518-0abcpz.step / ad9518-0abcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (64 pp, sha256 a72f757c560a37f4, retrieved 2026-10-28, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF