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AD9517-4ABCPZ

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Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD9517-4ABCPZ

Analog Devices · Clock Generators / Frequency Synthesizers / PLL · LFCSP-48(7x7)

AD9517-4ABCPZ from Analog Devices, in a LFCSP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REFMON output Reference monitor output, a 3.3 V CMOS pin with multiple selectable functions set by Register 0x01B.
2 LD output Lock detect output, a 3.3 V CMOS pin with multiple selectable functions set by Register 0x01A.
3 VCP power_in Charge pump supply, which must satisfy VS ≤ VCP ≤ 5.0 V; it is usually 3.3 V, but must be 5 V when a 5 V external VCXO is used.
4 CP output Charge pump output that connects to the external loop filter.
5 STATUS output Status output, a 3.3 V CMOS pin with multiple selectable functions set by Register 0x017.
6 REF_SEL input Reference select input that selects REF1 when low and REF2 when high, with an internal 30 kΩ pull-down resistor.
7 SYNC input Active-low input for manual synchronization and manual holdover, edge sensitive, with an internal 30 kΩ pull-up resistor.
8 LF input Loop filter input connected internally to the VCO control voltage node, with 31 pF of internal capacitance to ground that may affect loop filter design for large loop bandwidths.
9 BYPASS output Pin for bypassing the LDO to ground with a capacitor.
10 VS power_in 3.3 V power supply pin.
11 CLK input Complementary half of the self-biased differential clock input to the clock distribution section; it can be left floating when the internal VCO is used.
12 CLK input Complementary half of the self-biased differential clock input to the clock distribution section; it can be left floating when the internal VCO is used.
13 SCLK input Serial control port data clock input, a 3.3 V CMOS pin; write data is registered on its rising edge.
14 CS input Serial control port active-low chip select, a 3.3 V CMOS pin with an internal 30 kΩ pull-up resistor.
15 SDO output Serial control port unidirectional serial data output, used for readback only in unidirectional mode.
16 SDIO bidirectional Serial control port bidirectional serial data input/output, also used as unidirectional serial data input.
17 RESET input Active-low chip reset, a 3.3 V CMOS pin with an internal 30 kΩ pull-up resistor.
18 PD input Active-low chip power-down, a 3.3 V CMOS pin with an internal 30 kΩ pull-up resistor.
19 OUT2 output LVPECL output, one side of a differential LVPECL output pair (OUT2).
20 OUT2 output LVPECL output, the other side of the differential LVPECL output pair (OUT2).
21 VS_LVPECL power_in Extended-voltage LVPECL power pin, operating from 2.5 V to 3.3 V.
22 OUT3 output LVPECL output, one side of a differential LVPECL output pair (OUT3).
23 OUT3 output LVPECL output, the other side of the differential LVPECL output pair (OUT3).
24 VS power_in 3.3 V power supply pin.
25 VS power_in 3.3 V power supply pin.
26 OUT6 (OUT6A) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
27 OUT6 (OUT6B) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
28 OUT7 (OUT7A) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
29 OUT7 (OUT7B) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
30 VS power_in 3.3 V power supply pin.
31 VS power_in 3.3 V power supply pin.
32 OUT5 (OUT5B) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
33 OUT5 (OUT5A) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
34 OUT4 (OUT4B) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
35 OUT4 (OUT4A) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
36 VS power_in 3.3 V power supply pin.
37 VS power_in 3.3 V power supply pin.
38 OUT1 output LVPECL output, one side of a differential LVPECL output pair (OUT1).
39 OUT1 output LVPECL output, the other side of the differential LVPECL output pair (OUT1).
40 VS_LVPECL power_in Extended-voltage LVPECL power pin, operating from 2.5 V to 3.3 V.
41 OUT0 output LVPECL output, one side of a differential LVPECL output pair (OUT0).
42 OUT0 output LVPECL output, the other side of the differential LVPECL output pair (OUT0).
43 VS power_in 3.3 V power supply pin.
44 RSET passive Resistor connection that sets internal bias currents; nominal value is 4.12 kΩ.
45 VS power_in 3.3 V power supply pin.
46 CPRSET passive Resistor connection that sets the charge pump current range; nominal value is 5.1 kΩ.
47 REFIN (REF2) input Complementary half of the self-biased differential PLL reference input; alternatively a single-ended input for REF2.
48 REFIN (REF1) input Complementary half of the self-biased differential PLL reference input; alternatively a single-ended input for REF1.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-48(7x7)
Category RTC/Clock Chip
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VS VS 3.135 3.3 3.465 V 3.3 V ± 5% 4
LVPECL supply voltage VS_LVPECL 2.375 V Nominally 2.5 V to 3.3 V ± 5% 4
Charge pump supply voltage VCP 5.25 V Nominally 3.3 V to 5.0 V ± 5% 4
CPRSET pin resistor CPRSET 2.7 5.1 10 kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA); connect to ground 4
VCO frequency range 1450 1800 MHz See Figure 15 4
Tuning voltage VT VT 0.5 V VCP ≤ VS when using internal VCO; outside of this range, the CP spurs may increase due to CP up/down mismatch 4
Reference input frequency (differential) 0 250 MHz Differential mode; frequencies below about 1 MHz should be dc-coupled 4
Self-bias voltage REFIN (row 1) REFIN 1.35 1.6 1.75 V Self-bias voltage of REFIN1 4
Self-bias voltage REFIN (row 2) REFIN 1.3 1.5 1.6 V Self-bias voltage of REFIN1 4
Input resistance REFIN (row 1) REFIN 4 4.8 5.9 kΩ Self-biased 4
Input resistance REFIN (row 2) REFIN 4.4 5.3 6.4 kΩ Self-biased 4
Input frequency (AC-coupled), dual single-ended 20 250 MHz Slew rate > 50 V/µs 4
Input frequency (DC-coupled), dual single-ended 0 250 MHz Slew rate > 50 V/µs; CMOS levels 4
Input logic high 2 V 4
Input logic low 0.8 V 4
Input current -100 100 µA 4
PFD input frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns 4
PFD input frequency 45 MHz Antibacklash pulse width = 6.0 ns 4
Absolute accuracy 2.5 % CPV = VCP/2 V 5
Sink-and-source current matching 2 % 0.5 < CPV < VCP − 0.5 V 5
ICP vs. CPV 1.5 % 0.5 < CPV < VCP − 0.5 V 5
ICP vs. temperature 2 % CPV = VCP/2 V 5
ICP high impedance mode leakage 1 nA 5
Prescaler input frequency P=1 FD 300 MHz P = 1 FD 5
Prescaler input frequency P=2 FD 600 MHz P = 2 FD 5
Prescaler input frequency P=3 FD 900 MHz P = 3 FD 5
Prescaler input frequency P=2 DM (2/3) 200 MHz P = 2 DM (2/3) 5
Prescaler input frequency P=4 DM (4/5) 1000 MHz P = 4 DM (4/5) 5
Prescaler input frequency P=8 DM (8/9) 2400 MHz P = 8 DM (8/9) 5
LVPECL output frequency, maximum 2950 MHz Using direct to output; see Figure 25 6
LVPECL output differential voltage VOD 550 790 980 mV Default amplitude setting with driver not toggling; termination 50 Ω to VS − 2 V 6
LVDS output frequency 800 MHz The AD9517 outputs toggle at higher frequencies, but the output amplitude may not meet the VOD specification; see Figure 26 6
LVDS output differential voltage VOD 247 360 454 mV VOH − VOL at default amplitude setting with output driver not toggling; differential termination 100 Ω at 3.5 mA 6
Delta VOD 25 mV Absolute value of difference between VOD when normal output is high vs. complementary output is high 6
LVDS output offset voltage VOS 1.125 1.24 1.375 V (VOH + VOL)/2 across a differential pair 6
Delta VOS 25 mV Absolute value of difference between VOS when normal output is high vs. complementary output is high 6
Short-circuit current ISA, ISB 14 24 mA Output shorted to GND 6
CMOS output frequency 250 MHz Single-ended; termination = 10 pF; see Figure 27 7
CMOS output voltage low VOL 0.1 V At 1 mA load 7
CMOS source current, static 20 mA Static; exceeding these values can result in damage to the part 7
CMOS source current, dynamic 16 mA Dynamic; exceeding these values can result in damage to the part 7
CMOS sink current, static 8 mA Static; exceeding these values can result in damage to the part 7
CMOS sink current, dynamic 16 mA Dynamic; exceeding these values can result in damage to the part 7
LVPECL output rise time tRP 70 180 ps 20% to 80%, measured differentially; termination 50 Ω to VS − 2 V; level = 810 mV 8
Propagation delay CLK-to-LVPECL, high frequency clock distribution tPECL 835 995 1180 ps High frequency clock distribution configuration; see Figure 43 8
Propagation delay CLK-to-LVPECL, clock distribution tPECL 773 933 1090 ps Clock distribution configuration; see Figure 45 8
Propagation delay CLK-to-LVDS tLVDS 1.4 1.8 2.1 ns For all divide values; delay off on all outputs 8
Propagation delay CLK-to-CMOS tCMOS 1.6 2.1 2.6 ns For all divide values; fine delay off 8
SDO/SDIO output logic 1 voltage 2.7 V SDIO, SDO outputs 13
SDO/SDIO output logic 0 voltage 0.4 V SDIO, SDO outputs 13
Clock rate SCLK 1/tSCLK 25 MHz Serial control port timing 13
SCLK to valid SDIO and SDO tDV 8 ns Serial control port timing 13
Supply voltage VS to GND VS -0.3 3.6 V VS, VS_LVPECL to GND 17
Charge pump supply VCP to GND VCP -0.3 5.8 V VCP to GND 17
REFIN to REFIN differential REFIN -3.3 3.3 V REFIN to REFIN 17
Junction temperature TJ 150 °C 17
Storage temperature range -65 150 °C 17
Thermal resistance junction-to-ambient θJA 24.7 °C/W 48-lead LFCSP; 4-layer board in still air per EIA/JESD51-2 17

CAD (KiCad official)

  • Symbol: AD9517-4ABCPZ
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: LFCSP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ad9517-4abcpz-etched.step / ad9517-4abcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9517-4abcpz.step / ad9517-4abcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (80 pp, sha256 7e51d35117a7c7bb, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF