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AD9517-1ABCPZ-RL7

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Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipad9517-1abcpz-rl7factory-2.0.0extractor-text

Verified AD9517-1ABCPZ-RL7

by Ray · last 30 Oct 2026 · 1 record · files match
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Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD9517-1ABCPZ-RL7 · LFCSP-48(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 80-page datasheet
  • ✓distributor: lcsc C653508, digikey 505-AD9517-1ABCPZ-RL7TR-ND, mouser 584-AD9517-1ABCPZ-R7
  • ✓family: QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-jc32qmeh/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.79)
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad9517-1abcpz-rl7.kicad_sym✓ ad9517-1abcpz-rl7.kicad_mod✓ ad9517-1abcpz-rl7.step
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Contents

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AD9517-1ABCPZ-RL7

Analog Devices · Clock Generators / Frequency Synthesizers / PLL · LFCSP-48(7x7)

AD9517-1ABCPZ-RL7 from Analog Devices, in a LFCSP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REFMON output Reference monitor output on 3.3 V CMOS with multiple selectable outputs set by Register 0x01B.
2 LD output Lock detect output on 3.3 V CMOS with multiple selectable outputs set by Register 0x01A.
3 VCP power_in Power supply for the charge pump, which must satisfy VS ≤ VCP ≤ 5.0 V; it is usually 3.3 V but should be 5 V if a 5 V external VCXO is used.
4 CP output Charge pump output on 3.3 V CMOS that connects to the external loop filter.
5 STATUS output Status output on 3.3 V CMOS with multiple selectable outputs set by Register 0x017.
6 REF_SEL input Reference select input on 3.3 V CMOS that selects REF1 when low and REF2 when high, with an internal 30 kΩ pull-down resistor.
7 SYNC input Active-low 3.3 V CMOS input that initiates a manual synchronization and manual holdover, with an internal 30 kΩ pull-up resistor.
8 LF input Loop filter input that connects internally to the VCO control voltage node and has 31 pF of internal capacitance to ground, which may influence loop filter design for large loop bandwidths.
9 BYPASS passive Used for bypassing the LDO to ground with a capacitor.
10 VS power_in 3.3 V power pin.
11 CLK input Along with CLK, the self-biased differential input for the clock distribution section; it can be left floating if the internal VCO is used.
12 CLK input Along with CLK, the self-biased differential input for the clock distribution section; it can be left floating if the internal VCO is used.
13 SCLK input Serial control port data clock signal on 3.3 V CMOS.
14 CS input Active-low serial control port chip select on 3.3 V CMOS, with an internal 30 kΩ pull-up resistor.
15 SDO output Unidirectional serial control port data output on 3.3 V CMOS.
16 SDIO bidirectional Serial control port bidirectional serial data input/output on 3.3 V CMOS, also usable as a unidirectional serial data input.
17 RESET input Active-low chip reset on 3.3 V CMOS, with an internal 30 kΩ pull-up resistor.
18 PD input Active-low chip power-down on 3.3 V CMOS, with an internal 30 kΩ pull-up resistor.
19 OUT2 output LVPECL output; one side of a differential LVPECL output.
20 OUT2 output LVPECL output; one side of a differential LVPECL output.
21 VS_LVPECL power_in Extended voltage 2.5 V to 3.3 V LVPECL power pin.
22 OUT3 output LVPECL output; one side of a differential LVPECL output.
23 OUT3 output LVPECL output; one side of a differential LVPECL output.
24 VS power_in 3.3 V power pin.
25 VS power_in 3.3 V power pin.
26 OUT6 (OUT6A) output LVDS/CMOS output; one side of a differential LVDS output or a single-ended CMOS output.
27 OUT6 (OUT6B) output LVDS/CMOS output; one side of a differential LVDS output or a single-ended CMOS output.
28 OUT7 (OUT7A) output LVDS/CMOS output; one side of a differential LVDS output or a single-ended CMOS output.
29 OUT7 (OUT7B) output LVDS/CMOS output; one side of a differential LVDS output or a single-ended CMOS output.
30 VS power_in 3.3 V power pin.
31 VS power_in 3.3 V power pin.
32 OUT5 (OUT5B) output LVDS/CMOS output; one side of a differential LVDS output or a single-ended CMOS output.
33 OUT5 (OUT5A) output LVDS/CMOS output; one side of a differential LVDS output or a single-ended CMOS output.
34 OUT4 (OUT4B) output LVDS/CMOS output; one side of a differential LVDS output or a single-ended CMOS output.
35 OUT4 (OUT4A) output LVDS/CMOS output; one side of a differential LVDS output or a single-ended CMOS output.
36 VS power_in 3.3 V power pin.
37 VS power_in 3.3 V power pin.
38 OUT1 output LVPECL output; one side of a differential LVPECL output.
39 OUT1 output LVPECL output; one side of a differential LVPECL output.
40 VS_LVPECL power_in Extended voltage 2.5 V to 3.3 V LVPECL power pin.
41 OUT0 output LVPECL output; one side of a differential LVPECL output.
42 OUT0 output LVPECL output; one side of a differential LVPECL output.
43 VS power_in 3.3 V power pin.
44 RSET passive Resistor connected here sets internal bias currents; nominal value is 4.12 kΩ.
45 VS power_in 3.3 V power pin.
46 CPRSET passive Resistor connected here sets the charge pump current range; nominal value is 5.1 kΩ.
47 REFIN (REF2) input Along with REFIN, the self-biased differential input for the PLL reference; alternatively, a single-ended input for REF2.
48 REFIN (REF1) input Along with REFIN, the self-biased differential input for the PLL reference; alternatively, a single-ended input for REF1.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-48(7x7)
Category RTC/Clock Chip
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VS, 3.3 V power supply VS 3.135 3.3 3.465 V 3.3 V ± 5% 4
VS_LVPECL, LVPECL power supply (max printed as VS) VS_LVPECL 2.375 V Nominally 2.5 V to 3.3 V ± 5% 4
VCP, charge pump supply (min printed as VS) VCP 5.25 V Nominally 3.3 V to 5.0 V ± 5% 4
CPRSET Pin Resistor CPRSET 2.7 5.1 10 kΩ Sets internal CP current range, nominally 4.8 mA 4
VCO Frequency Range 2300 2650 MHz See Figure 15 4
Tuning Voltage (VT) (max printed as VCP − 0.5 V) VT 0.5 V VCP ≤ VS when using internal VCO 4
Input Frequency, differential REFIN mode 0 250 MHz Differential mode; below about 1 MHz should be dc-coupled 4
Self-Bias Voltage, REFIN (first row as printed) 1.35 1.6 1.75 V Self-bias voltage of REFIN (footnote 1) 4
Self-Bias Voltage, REFIN (second row as printed) 1.3 1.5 1.6 V Self-bias voltage of REFIN (footnote 1) 4
Input Resistance, REFIN (first row as printed) 4 4.8 5.9 kΩ Self-biased 4
Input Resistance, REFIN (second row as printed) 4.4 5.3 6.4 kΩ Self-biased 4
Input Frequency (AC-Coupled), dual single-ended mode 20 250 MHz Slew rate > 50 V/μs 4
Input Frequency (DC-Coupled), dual single-ended mode 0 250 MHz Slew rate > 50 V/μs; CMOS levels 4
Input Current (REF1/REF2) -100 100 μA 4
PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns 4
PFD Input Frequency 45 MHz Antibacklash pulse width = 6.0 ns 4
CPRSET Range CPRSET 2.7 10 kΩ 5
Input Frequency, CLK/CLK high frequency distribution 0 2.4 GHz High frequency distribution (VCO divider) 6
Input Frequency, CLK/CLK distribution only 0 1.6 GHz Distribution only (VCO divider bypassed) 6
Input Common-Mode Voltage, VCM VCM 1.3 1.57 1.8 V Self-biased; enables ac coupling 6
Input Common-Mode Range, VCMR VCMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled 6
Input Resistance, CLK/CLK 3.9 4.7 5.7 kΩ Self-biased 6
LVPECL Output Frequency, Maximum 2950 MHz Using direct to output 6
Output High Voltage (VOH), printed as VS_LVPECL − x V VOH -1.12 -0.98 -0.84 V Termination = 50 Ω to VS − 2 V 6
Output Low Voltage (VOL), printed as VS_LVPECL − x V VOL -2.03 -1.77 -1.49 V Termination = 50 Ω to VS − 2 V 6
Output Differential Voltage (VOD), LVPECL VOD 550 790 980 mV Default amplitude setting; driver not toggling 6
Output Differential Voltage (VOD), LVDS VOD 247 360 454 mV Default amplitude setting; output driver not toggling; differential termination 100 Ω 6
Output Offset Voltage (VOS), LVDS VOS 1.125 1.24 1.375 V (VOH + VOL)/2 across a differential pair 6
PROPAGATION DELAY, tPECL, CLK-to-LVPECL, high frequency clock distribution configuration tPECL 835 995 1180 ps See Figure 43 8
PROPAGATION DELAY, tPECL, CLK-to-LVPECL, clock distribution configuration tPECL 773 933 1090 ps See Figure 45 8
PROPAGATION DELAY, tLVDS, CLK-to-LVDS output tLVDS 1.4 1.8 2.1 ns For all divide values; delay off on all outputs 8
PROPAGATION DELAY, tCMOS, CLK-to-CMOS output tCMOS 1.6 2.1 2.6 ns For all divide values; fine delay off 8
DELAY ADJUST, Shortest Delay Range, Zero Scale 50 315 680 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b 8
DELAY ADJUST, Shortest Delay Range, Full Scale 540 880 1180 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b 8
DELAY ADJUST, Longest Delay Range, Zero Scale 200 570 950 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b 8
DELAY ADJUST, Longest Delay Range, Quarter Scale 1.72 2.31 2.89 ns Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 001100b 8
DELAY ADJUST, Longest Delay Range, Full Scale 5.7 8 10.1 ns Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b 8
VS, VS_LVPECL to GND -0.3 3.6 V 17
VCP to GND VCP -0.3 5.8 V 17
REFIN, REFIN to GND (max printed as VS + 0.3 V) -0.3 V 17
REFIN to REFIN -3.3 3.3 V 17
RSET to GND (max printed as VS + 0.3 V) -0.3 V 17
CPRSET to GND (max printed as VS + 0.3 V) -0.3 V 17
CLK, CLK to GND (max printed as VS + 0.3 V) -0.3 V 17
CLK to CLK -1.2 1.2 V 17
SCLK, SDIO, SDO, CS to GND (max printed as VS + 0.3 V) -0.3 V 17
OUT0 to OUT7 (complements) to GND (max printed as VS + 0.3 V) -0.3 V 17
SYNC to GND (max printed as VS + 0.3 V) -0.3 V 17
REFMON, STATUS, LD to GND (max printed as VS + 0.3 V) -0.3 V 17
Junction Temperature 150 °C See Table 19 for θJA 17
Storage Temperature Range -65 150 °C 17
Lead Temperature 300 °C 10 sec 17
CMOS Output Source Current, Static 20 mA Static; exceeding this value can result in damage 7
CMOS Output Source Current, Dynamic 16 mA Dynamic; exceeding this value can result in damage 7
CMOS Output Sink Current, Static 8 mA Static; exceeding this value can result in damage 7
CMOS Output Sink Current, Dynamic 16 mA Dynamic; exceeding this value can result in damage 7
Operating Ambient Temperature (TA) TA -40 85 °C Min/max specified over full VS and TA range (industrial) 4
Thermal Resistance, junction-to-ambient, 48-lead LFCSP θJA 24.7 °C/W 4-layer board, still air, EIA/JESD51-2 17

CAD (KiCad official)

  • Symbol: AD9517-1ABCPZ-RL7
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: LFCSP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ad9517-1abcpz-rl7-etched.step / ad9517-1abcpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9517-1abcpz-rl7.step / ad9517-1abcpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (80 pp, sha256 e35c86d638f76dc7, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF