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AD9516-5BCPZ

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Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD9516-5BCPZ

Analog Devices · Clock Generators / Frequency Synthesizers / PLL · LFCSP-64(9x9)

AD9516-5BCPZ from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VS power_in 3.3 V power supply pin.
2 REFMON output 3.3 V CMOS reference monitor output with multiple selectable functions.
3 LD output 3.3 V CMOS lock detect output with multiple selectable functions.
4 VCP power_in Charge pump supply, with VS ≤ VCP ≤ 5.25 V.
5 CP output Charge pump output that connects to an external loop filter; it can be left unconnected if the PLL is not used.
6 STATUS output 3.3 V CMOS status output with multiple selectable functions.
7 REF_SEL input 3.3 V CMOS reference select; low selects REF1 and high selects REF2, with an internal 30 kΩ pull-down.
8 SYNC input 3.3 V CMOS active-low input for manual synchronization and manual holdover, with an internal 30 kΩ pull-up.
9 NC unconnected No connection; can be left floating.
10 NC unconnected No connection; can be left floating.
11 VS power_in 3.3 V power supply pin.
12 VS power_in 3.3 V power supply pin.
13 CLK input True side of the differential clock input for the clock distribution section.
14 CLK input Complement side of the differential clock input; for a single-ended input, connect a 0.1 μF bypass capacitor from CLK to ground.
15 NC unconnected No connection; can be left floating.
16 SCLK input 3.3 V CMOS serial control port data clock input.
17 CS input 3.3 V CMOS serial control port chip select, active low, with an internal 30 kΩ pull-up.
18 NC unconnected No connection; can be left floating.
19 NC unconnected No connection; can be left floating.
20 NC unconnected No connection; can be left floating.
21 SDO output 3.3 V CMOS serial data output, used only in unidirectional serial mode.
22 SDIO bidirectional 3.3 V CMOS serial control port bidirectional serial data input/output.
23 RESET input 3.3 V CMOS chip reset, active low, with an internal 30 kΩ pull-up.
24 PD input 3.3 V CMOS chip power-down, active low, with an internal 30 kΩ pull-up.
25 OUT4 output LVPECL output, one side of a differential LVPECL output up to 1.6 GHz.
26 OUT4 output LVPECL output, complement side of a differential LVPECL output up to 1.6 GHz.
27 VS_LVPECL power_in Extended 2.5 V to 3.3 V LVPECL power supply pin.
28 OUT5 output LVPECL output, one side of a differential LVPECL output up to 1.6 GHz.
29 OUT5 output LVPECL output, complement side of a differential LVPECL output up to 1.6 GHz.
30 VS power_in 3.3 V power supply pin.
31 VS power_in 3.3 V power supply pin.
32 VS power_in 3.3 V power supply pin.
33 OUT8 (OUT8A) output LVDS output side up to 800 MHz, or a single-ended CMOS output up to 250 MHz.
34 OUT8 (OUT8B) output LVDS output side up to 800 MHz, or a single-ended CMOS output up to 250 MHz.
35 OUT9 (OUT9A) output LVDS output side up to 800 MHz, or a single-ended CMOS output up to 250 MHz.
36 OUT9 (OUT9B) output LVDS output side up to 800 MHz, or a single-ended CMOS output up to 250 MHz.
37 GND power_in Ground pin; the exposed paddle on the package bottom must be connected to ground for proper operation.
38 VS power_in 3.3 V power supply pin.
39 OUT3 output LVPECL output, one side of a differential LVPECL output up to 1.6 GHz.
40 OUT3 output LVPECL output, complement side of a differential LVPECL output up to 1.6 GHz.
41 VS_LVPECL power_in Extended 2.5 V to 3.3 V LVPECL power supply pin.
42 OUT2 output LVPECL output, one side of a differential LVPECL output up to 1.6 GHz.
43 OUT2 output LVPECL output, complement side of a differential LVPECL output up to 1.6 GHz.
44 GND power_in Ground pin.
45 OUT7 (OUT7B) output LVDS output side up to 800 MHz, or a single-ended CMOS output up to 250 MHz.
46 OUT7 (OUT7A) output LVDS output side up to 800 MHz, or a single-ended CMOS output up to 250 MHz.
47 OUT6 (OUT6B) output LVDS output side up to 800 MHz, or a single-ended CMOS output up to 250 MHz.
48 OUT6 (OUT6A) output LVDS output side up to 800 MHz, or a single-ended CMOS output up to 250 MHz.
49 VS power_in 3.3 V power supply pin.
50 VS power_in 3.3 V power supply pin.
51 VS power_in 3.3 V power supply pin.
52 OUT1 output LVPECL output, one side of a differential LVPECL output up to 1.6 GHz.
53 OUT1 output LVPECL output, complement side of a differential LVPECL output up to 1.6 GHz.
54 VS_LVPECL power_in Extended 2.5 V to 3.3 V LVPECL power supply pin.
55 OUT0 output LVPECL output, one side of a differential LVPECL output up to 1.6 GHz.
56 OUT0 output LVPECL output, complement side of a differential LVPECL output up to 1.6 GHz.
57 VS power_in 3.3 V power supply pin.
58 RSET passive Resistor connected to this pin sets internal bias currents; nominal value 4.12 kΩ.
59 GND power_in Ground pin.
60 VS power_in 3.3 V power supply pin.
61 VS power_in 3.3 V power supply pin.
62 CPRSET passive Resistor sets the charge pump current range; nominal value 5.1 kΩ, and it can be omitted if the PLL is not used.
63 REFIN (REF2) input Complement of the differential PLL reference input, or the single-ended REF2 input; can be left unconnected when the PLL is not used.
64 REFIN (REF1) input True side of the differential PLL reference input, or the single-ended REF1 input; can be left unconnected when the PLL is not used.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-64(9x9)
Category RTC/Clock Chip
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VS VS 3.135 3.3 3.465 V 3.3 V ± 5% 4
LVPECL supply voltage VS_LVPECL 2.375 V Nominally 2.5 V to 3.3 V ± 5% 4
Charge pump supply voltage VCP 5.25 V Nominally 3.3 V to 5.0 V ± 5% 4
CPRSET pin resistor CPRSET 2.7 5.1 10 kΩ Sets internal CP current range, nominally 4.8 mA 4
Operating temperature range TA -40 85 °C Industrial range; min and max given over full VS and TA variation 4
Differential reference input frequency REFIN 0 250 MHz Differential mode; frequencies below about 1 MHz should be dc-coupled 4
Self-bias voltage, REFIN REFIN 1.35 1.6 1.75 V Self-bias voltage of REFIN 4
Self-bias voltage, REFIN (second row) REFIN 1.3 1.5 1.6 V Self-bias voltage of REFIN 4
Input resistance, REFIN REFIN 4 4.8 5.9 kΩ Self-biased 4
Input resistance, REFIN (second row) REFIN 4.4 5.3 6.4 kΩ Self-biased 4
Input current, single-ended reference inputs -100 100 μA Dual single-ended mode, REF1/REF2 4
Clock input frequency CLK 0 2.4 GHz High frequency distribution (VCO divider enabled) 6
Clock input frequency (distribution only) CLK 0 1.6 GHz Distribution only (VCO divider bypassed) 6
Input common-mode voltage VCM 1.3 1.57 1.8 V Self-biased; enables ac coupling 6
Clock input resistance 3.9 4.7 5.7 kΩ Self-biased 6
LVPECL output differential voltage VOD 550 790 980 mV Default amplitude setting, driver not toggling 6
LVDS output differential voltage VOD 247 360 454 mV Default amplitude setting, output driver not toggling 6
LVDS output offset voltage VOS 1.125 1.24 1.375 V Default amplitude setting, output driver not toggling 6
Power dissipation, power-on default 1 1.2 W No clock; no programming; default register values 11
Power dissipation, full operation 1.5 2.1 W fCLK = 2.25 GHz; VCO divider = 2; all channel dividers on 11
Supply voltage VS to GND VS, VS_LVPECL -0.3 3.6 V To GND 15
Charge pump supply voltage to GND VCP -0.3 5.8 V To GND 15
REFIN to REFIN voltage REFIN -3.3 3.3 V REFIN to REFIN 15
CLK to CLK voltage CLK -1.2 1.2 V CLK to CLK 15
Junction temperature TJ 150 °C See Table 16 for θJA 15
Storage temperature range TSTG -65 150 °C Storage 15
Lead temperature 300 °C 10 sec 15
Thermal resistance, junction to ambient, 64-lead LFCSP θJA 22 °C/W 4-layer board in still air per EIA/JESD51-2 15

CAD (KiCad official)

  • Symbol: AD9516-5BCPZ
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: ad9516-5bcpz-etched.step / ad9516-5bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9516-5bcpz.step / ad9516-5bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (76 pp, sha256 579e9126f5342bbd, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF