component

AD9516-2BCPZ

Public Made by Adom

by adom

Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipad9516-2bcpzfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

AD9516-2BCPZ

Analog Devices · Clock Generators / Frequency Synthesizers / PLL · LFCSP-64(9x9)

AD9516-2BCPZ from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VS power_in 3.3 V power pin.
2 REFMON output Reference monitor output with multiple selectable outputs set by Register 0x01B.
3 LD output Lock detect 3.3 V CMOS output with multiple selectable outputs set by Register 0x01A.
4 VCP power_in Charge pump supply, with VS ≤ VCP ≤ 5.0 V.
5 CP output Charge pump output that connects to the external loop filter.
6 STATUS output 3.3 V CMOS status output with multiple selectable outputs set by Register 0x017.
7 REF_SEL input Reference select: low selects REF1 and high selects REF2, with an internal 30 kΩ pull-down.
8 SYNC input Active-low manual synchronization and manual holdover input with an internal 30 kΩ pull-up.
9 LF input Loop filter input connected internally to the VCO control voltage node, with 31 pF of internal capacitance to ground.
10 BYPASS passive Bypasses the LDO to ground with a capacitor.
11 VS power_in 3.3 V power pin.
12 VS power_in 3.3 V power pin.
13 CLK input Along with the complementary CLK pin, forms the differential clock input for the clock distribution section.
14 CLK input Along with the complementary CLK pin, forms the differential clock input for the clock distribution section.
15 NC unconnected No connect; do not connect to this pin.
16 SCLK input Serial control port data clock input, 3.3 V CMOS.
17 CS input Serial control port chip select, active low, with an internal 30 kΩ pull-up to VS.
18 NC unconnected No connect; do not connect to this pin.
19 NC unconnected No connect; do not connect to this pin.
20 NC unconnected No connect; do not connect to this pin.
21 SDO output Serial control port unidirectional serial data output, used only in unidirectional I/O mode.
22 SDIO bidirectional Serial control port bidirectional serial data input/output; default mode.
23 RESET input Chip reset, active low, with an internal 30 kΩ pull-up.
24 PD input Chip power-down, active low, with an internal 30 kΩ pull-up.
25 OUT4 output LVPECL output, one side of differential LVPECL output pair OUT4.
26 OUT4 output LVPECL output, one side of differential LVPECL output pair OUT4.
27 VS_LVPECL power_in Extended voltage 2.5 V to 3.3 V LVPECL power pin.
28 OUT5 output LVPECL output, one side of differential LVPECL output pair OUT5.
29 OUT5 output LVPECL output, one side of differential LVPECL output pair OUT5.
30 VS power_in 3.3 V power pin.
31 VS power_in 3.3 V power pin.
32 VS power_in 3.3 V power pin.
33 OUT8 (OUT8A) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
34 OUT8 (OUT8B) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
35 OUT9 (OUT9A) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
36 OUT9 (OUT9B) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
37 GND power_in Ground pin; the external paddle on the package bottom must also be connected to ground.
38 VS power_in 3.3 V power pin.
39 OUT3 output LVPECL output, one side of differential LVPECL output pair OUT3.
40 OUT3 output LVPECL output, one side of differential LVPECL output pair OUT3.
41 VS_LVPECL power_in Extended voltage 2.5 V to 3.3 V LVPECL power pin.
42 OUT2 output LVPECL output, one side of differential LVPECL output pair OUT2.
43 OUT2 output LVPECL output, one side of differential LVPECL output pair OUT2.
44 GND power_in Ground pin; the external paddle on the package bottom must also be connected to ground.
45 OUT7 (OUT7B) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
46 OUT7 (OUT7A) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
47 OUT6 (OUT6B) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
48 OUT6 (OUT6A) output LVDS or CMOS output, one side of a differential LVDS output or a single-ended CMOS output.
49 VS power_in 3.3 V power pin.
50 VS power_in 3.3 V power pin.
51 VS power_in 3.3 V power pin.
52 OUT1 output LVPECL output, one side of differential LVPECL output pair OUT1.
53 OUT1 output LVPECL output, one side of differential LVPECL output pair OUT1.
54 VS_LVPECL power_in Extended voltage 2.5 V to 3.3 V LVPECL power pin.
55 OUT0 output LVPECL output, one side of differential LVPECL output pair OUT0.
56 OUT0 output LVPECL output, one side of differential LVPECL output pair OUT0.
57 VS power_in 3.3 V power pin.
58 RSET passive Resistor connected to this pin sets internal bias currents; nominal value 4.12 kΩ.
59 GND power_in Ground pin; the external paddle on the package bottom must also be connected to ground.
60 VS power_in 3.3 V power pin.
61 VS power_in 3.3 V power pin.
62 CPRSET passive Resistor connected to this pin sets the charge pump current range; nominal value 5.1 kΩ.
63 REFIN (REF2) input With REFIN, forms the differential PLL reference input; alternatively a single-ended REF2 input.
64 REFIN (REF1) input With REFIN, forms the differential PLL reference input; alternatively a single-ended REF1 input.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-64(9x9)
Category RTC/Clock Chip
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VS VS 3.135 3.3 3.465 V 3.3 V ± 5% 4
LVPECL supply voltage VS_LVPECL VS_LVPECL 2.375 V Nominally 2.5 V to 3.3 V ± 5%; max printed as VS 4
Charge pump supply VCP VCP 5.25 V Nominally 3.3 V to 5.0 V ± 5%; min printed as VS 4
Ambient operating temperature TA -40 85 °C Standard industrial range 4
CPRSET pin resistor CPRSET 2.7 5.1 10 kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA); connect to ground 4
VCO frequency range 2050 2335 MHz See Figure 15 4
Tuning voltage VT VT 0.5 V VCP ≤ VS when using internal VCO; max printed as VCP − 0.5; outside this range CP spurs may increase 4
REFIN input frequency 0 250 MHz Differential mode; frequencies below about 1 MHz should be dc-coupled 4
Self-bias voltage REFIN 1.35 1.6 1.75 V Self-bias voltage of REFIN1 4
Self-bias voltage REFIN (second row) 1.3 1.5 1.6 V Self-bias voltage of REFIN1 4
Input resistance REFIN 4 4.8 5.9 kΩ Self-biased1 4
Input resistance REFIN (second row) 4.4 5.3 6.4 kΩ Self-biased1 4
Input frequency AC-coupled (dual single-ended) 20 250 MHz Slew rate > 50 V/µs 4
Input frequency DC-coupled (dual single-ended) 0 250 MHz Slew rate > 50 V/µs; CMOS levels 4
Input logic high (REF1/REF2) 2 V 4
Input logic low (REF1/REF2) 0.8 V 4
Input current (REF1/REF2) -100 100 µA 4
PFD input frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns 4
PFD input frequency (6.0 ns pulse) 45 MHz Antibacklash pulse width = 6.0 ns 4
ICP sink/source high value ICP 4.8 mA With CPRSET = 5.1 kΩ 5
ICP sink/source low value ICP 0.6 mA 5
CLK input frequency (VCO divider) 0 2.4 GHz High frequency distribution (VCO divider) 6
CLK input frequency (VCO divider bypassed) 0 1.6 GHz Distribution only (VCO divider bypassed) 6
Input common-mode voltage VCM VCM 1.3 1.57 1.8 V Self-biased; enables ac coupling 6
Input common-mode range VCMR VCMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled 6
LVPECL output frequency maximum 2950 MHz Using direct to output; see Figure 25 for peak-to-peak differential amplitude 6
LVPECL differential output voltage VOD VOD 550 790 980 mV VOH − VOL for each leg of a differential pair for default amplitude setting with driver not toggling; see Figure 25 for variation over frequency 6
LVDS output frequency 800 MHz The AD9516 outputs toggle at higher frequencies, but the output amplitude may not meet the VOD specification; see Figure 26 6
LVDS differential output voltage VOD VOD 247 360 454 mV VOH − VOL measurement across a differential pair at the default amplitude setting with output driver not toggling; see Figure 26 6
LVDS output offset voltage VOS VOS 1.125 1.24 1.375 V (VOH + VOL)/2 across a differential pair 6
CMOS output frequency 250 MHz Single-ended; termination = 10 pF 6
CMOS output voltage low VOL VOL 0.1 V At 1 mA load 6
LVPECL propagation delay (high frequency clock distribution) tPECL 835 995 1180 ps See Figure 43 7
LVPECL propagation delay (clock distribution configuration) tPECL 773 933 1090 ps See Figure 45 7
LVDS propagation delay tLVDS 1.4 1.8 2.1 ns For All Divide Values; delay off on all outputs 7
CMOS propagation delay tCMOS 1.6 2.1 2.6 ns For All Divide Values; fine delay off 7
Delay adjust shortest range zero scale 50 315 680 ps Shortest delay range; Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b 7
Delay adjust shortest range full scale 540 880 1180 ps Shortest delay range; Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b 7
Delay adjust longest range zero scale 200 570 950 ps Longest delay range; Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b 7
Delay adjust longest range quarter scale 1.72 2.31 2.89 ns Longest delay range; Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 001100b 7
Delay adjust longest range full scale 5.7 8 10.1 ns Longest delay range; Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b 7
CS input logic 1 voltage 2 V CS (input) 12
CS input logic 0 voltage 0.8 V CS (input) 12
SDIO input logic 1 voltage 2 V SDIO (when input) 12
SDIO input logic 0 voltage 0.8 V SDIO (when input) 12
SDIO, SDO output logic 1 voltage 2.7 V SDIO, SDO (outputs) 12
SDIO, SDO output logic 0 voltage 0.4 V SDIO, SDO (outputs) 12
Serial clock rate SCLK 25 MHz Clock rate (SCLK, 1/tSCLK) 12
SCLK pulse width high tHIGH 16 ns 12
SCLK pulse width low tLOW 16 ns 12
CS minimum pulse width high tPWH 3 ns 12
RESET pulse width low 50 ns RESET timing 13
PD, RESET, SYNC input logic 1 voltage 2 V Input characteristics; each pin has 30 kΩ internal pull-up resistor 13
PD, RESET, SYNC input logic 0 voltage 0.8 V Input characteristics; each pin has 30 kΩ internal pull-up resistor 13
LD, STATUS, REFMON output voltage high VOH 2.7 V When selected as a digital output (CMOS) 13
LD, STATUS, REFMON output voltage low VOL 0.4 V When selected as a digital output (CMOS) 13
LD, STATUS, REFMON maximum toggle rate 100 MHz Applies when mux is set to any divider or counter output, or PFD up/down pulse 13
Supply voltage VS (absolute maximum) VS -0.3 3.6 V VS, VS_LVPECL to GND 16
Charge pump supply VCP (absolute maximum) VCP -0.3 5.8 V VCP to GND 16
REFIN to REFIN voltage -3.3 3.3 V REFIN to REFIN 16
CLK to CLK voltage -1.2 1.2 V CLK to CLK 16
Junction temperature TJ 150 °C 16
Storage temperature range -65 150 °C 16
Lead temperature 300 °C 10 sec 16
Thermal resistance junction-to-ambient θJA θJA 24 °C/W 64-Lead LFCSP; 4-layer board in still air per EIA/JESD51-2 16

CAD (KiCad official)

  • Symbol: AD9516-2BCPZ
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: ad9516-2bcpz-etched.step / ad9516-2bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9516-2bcpz.step / ad9516-2bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (80 pp, sha256 edb7fd699834bbb4, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF