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AD9516-1BCPZ-REEL7

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Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timingad9516-1bcpz-reel7factory-2.0.0extractor-text

Verified AD9516-1BCPZ-REEL7

by Ray · last 30 Oct 2026 · 1 record · files match
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Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD9516-1BCPZ-REEL7 · LFCSP-64(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 80-page datasheet
  • ✓distributor: lcsc C514287, digikey 505-AD9516-1BCPZ-REEL7TR-ND, mouser 584-AD9516-1BCPZR7
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-h98_a9kn/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.80)
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad9516-1bcpz-reel7.kicad_sym✓ ad9516-1bcpz-reel7.kicad_mod✓ ad9516-1bcpz-reel7.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers ad9516-1bcpz-reel7: viewers · Ray 5d ago
ad9516-1bcpz-reel7-etched.glb Publish 0.1.0 · Ray 5d ago
ad9516-1bcpz-reel7-etched.step ad9516-1bcpz-reel7: factory component page (tier=mfr) · Ray 5d ago
ad9516-1bcpz-reel7-hero.glb ad9516-1bcpz-reel7: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
ad9516-1bcpz-reel7-hero.overlay.json Publish 0.1.0 · Ray 5d ago
ad9516-1bcpz-reel7.glb Publish 0.1.0 · Ray 5d ago
ad9516-1bcpz-reel7.kicad_mod Publish 0.1.0 · Ray 5d ago
ad9516-1bcpz-reel7.kicad_sym Publish 0.1.0 · Ray 5d ago
ad9516-1bcpz-reel7.lbr Publish 0.1.0 · Ray 5d ago
ad9516-1bcpz-reel7.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
verification.json Verified: Published by the parts factory: tier mfr, 65 pins · Ray 5d ago

AD9516-1BCPZ-REEL7

Analog Devices · Clock Generators / Frequency Synthesizers / PLL · LFCSP-64(9x9)

AD9516-1BCPZ-REEL7 from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VS power_in 3.3 V power supply pin.
2 REFMON output Reference monitor 3.3 V CMOS output with multiple selectable functions, set in Register 0x01B.
3 LD output Lock detect 3.3 V CMOS output with multiple selectable functions, set in Register 0x1A.
4 VCP power_in Charge pump power supply, which must satisfy VS ≤ VCP ≤ 5.0 V.
5 CP output 3.3 V CMOS charge pump output that connects to the external loop filter.
6 STATUS output 3.3 V CMOS status output with multiple selectable outputs, set in Register 0x017.
7 REF_SEL input 3.3 V CMOS reference select that selects REF1 when low and REF2 when high, with an internal 30 kΩ pull-down.
8 SYNC input 3.3 V CMOS active-low input for manual synchronization and manual holdover, with an internal 30 kΩ pull-up.
9 LF input Loop filter input connected internally to the VCO control voltage node, with 31 pF of internal capacitance to ground that may affect loop filter design above 500 kHz loop bandwidth.
10 BYPASS passive Pin for bypassing the LDO to ground with a capacitor.
11 VS power_in 3.3 V power supply pin.
12 VS power_in 3.3 V power supply pin.
13 CLK input Together with CLK, the differential input for the clock distribution section.
14 CLK input Together with CLK, the differential input for the clock distribution section.
15 NC unconnected No connect; do not connect to this pin.
16 SCLK input 3.3 V CMOS serial control port data clock signal.
17 CS input 3.3 V CMOS serial control port chip select, active low, with an internal 30 kΩ pull-up to VS.
18 NC unconnected No connect; do not connect to this pin.
19 NC unconnected No connect; do not connect to this pin.
20 NC unconnected No connect; do not connect to this pin.
21 SDO output 3.3 V CMOS serial control port unidirectional serial data out, used only in unidirectional I/O mode.
22 SDIO bidirectional 3.3 V CMOS serial control port bidirectional serial data input/output.
23 RESET input 3.3 V CMOS chip reset, active low, with an internal 30 kΩ pull-up.
24 PD input 3.3 V CMOS chip power-down, active low, with an internal 30 kΩ pull-up.
25 OUT4 output LVPECL output; one side of a differential LVPECL output.
26 OUT4 output LVPECL output; one side of a differential LVPECL output.
27 VS_LVPECL power_in Extended voltage 2.5 V to 3.3 V LVPECL power pin.
28 OUT5 output LVPECL output; one side of a differential LVPECL output.
29 OUT5 output LVPECL output; one side of a differential LVPECL output.
30 VS power_in 3.3 V power supply pin.
31 VS power_in 3.3 V power supply pin.
32 VS power_in 3.3 V power supply pin.
33 OUT8 (OUT8A) output LVDS/CMOS output; one side of a differential LVDS output, or a single-ended CMOS output.
34 OUT8 (OUT8B) output LVDS/CMOS output; one side of a differential LVDS output, or a single-ended CMOS output.
35 OUT9 (OUT9A) output LVDS/CMOS output; one side of a differential LVDS output, or a single-ended CMOS output.
36 OUT9 (OUT9B) output LVDS/CMOS output; one side of a differential LVDS output, or a single-ended CMOS output.
37 GND power_in Ground pin; the external paddle on the bottom of the package must be connected to ground for proper operation.
38 VS power_in 3.3 V power supply pin.
39 OUT3 output LVPECL output; one side of a differential LVPECL output.
40 OUT3 output LVPECL output; one side of a differential LVPECL output.
41 VS_LVPECL power_in Extended voltage 2.5 V to 3.3 V LVPECL power pin.
42 OUT2 output LVPECL output; one side of a differential LVPECL output.
43 OUT2 output LVPECL output; one side of a differential LVPECL output.
44 GND power_in Ground pin; the external paddle on the bottom of the package must be connected to ground for proper operation.
45 OUT7 (OUT7B) output LVDS/CMOS output; one side of a differential LVDS output, or a single-ended CMOS output.
46 OUT7 (OUT7A) output LVDS/CMOS output; one side of a differential LVDS output, or a single-ended CMOS output.
47 OUT6 (OUT6B) output LVDS/CMOS output; one side of a differential LVDS output, or a single-ended CMOS output.
48 OUT6 (OUT6A) output LVDS/CMOS output; one side of a differential LVDS output, or a single-ended CMOS output.
49 VS power_in 3.3 V power supply pin.
50 VS power_in 3.3 V power supply pin.
51 VS power_in 3.3 V power supply pin.
52 OUT1 output LVPECL output; one side of a differential LVPECL output.
53 OUT1 output LVPECL output; one side of a differential LVPECL output.
54 VS_LVPECL power_in Extended voltage 2.5 V to 3.3 V LVPECL power pin.
55 OUT0 output LVPECL output; one side of a differential LVPECL output.
56 OUT0 output LVPECL output; one side of a differential LVPECL output.
57 VS power_in 3.3 V power supply pin.
58 RSET passive A resistor connected to this pin sets internal bias currents; nominal value 4.12 kΩ.
59 GND power_in Ground pin; the external paddle on the bottom of the package must be connected to ground for proper operation.
60 VS power_in 3.3 V power supply pin.
61 VS power_in 3.3 V power supply pin.
62 CPRSET passive A resistor connected to this pin sets the charge pump current range; nominal value 5.1 kΩ.
63 REFIN (REF2) input Together with REFIN, the differential PLL reference input; alternatively a single-ended input for REF2.
64 REFIN (REF1) input Together with REFIN, the differential PLL reference input; alternatively a single-ended input for REF1.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-64(9x9)
Category Clock and Timing
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VS supply voltage VS 3.135 3.3 3.465 V 3.3 V ± 5% 4
VS_LVPECL LVPECL supply voltage VS_LVPECL 2.375 V Nominally 2.5 V to 3.3 V ± 5%; printed max is VS (not numeric) 4
VCP charge pump supply voltage VCP 5.25 V Nominally 3.3 V to 5.0 V ± 5%; printed min is VS (not numeric) 4
CPRSET pin resistor CPRSET 2.7 5.1 10 kΩ Sets CP current range; connect to ground 4
VCO (on-chip) frequency range 2300 2650 MHz See Figure 15 4
Tuning voltage (VT) VT 0.5 V VCP ≤ VS when using internal VCO; printed max is VCP − 0.5 (not numeric) 4
Differential reference input frequency REFIN 0 250 MHz Differential mode; frequencies below about 1 MHz should be dc-coupled 4
Self-bias voltage, REFIN 1.35 1.6 1.75 V Self-bias voltage of REFIN1 4
Self-bias voltage, REFIN complement (bar lost in text) 1.3 1.5 1.6 V Self-bias voltage of REFIN1 4
Input resistance, REFIN 4 4.8 5.9 kΩ Self-biased 4
Input resistance, REFIN complement (bar lost in text) 4.4 5.3 6.4 kΩ Self-biased 4
Input frequency, AC-coupled single-ended (REF1/REF2) 20 250 MHz Slew rate > 50 V/µs 4
Input frequency, DC-coupled single-ended (REF1/REF2) 0 250 MHz Slew rate > 50 V/µs; CMOS levels 4
Input current (REF1/REF2) -100 100 µA 4
CLK input frequency, high frequency distribution CLK 0 2.4 GHz High frequency distribution (VCO divider) 6
CLK input frequency, distribution only CLK 0 1.6 GHz Distribution only (VCO divider bypassed) 6
Input common-mode voltage, VCM VCM 1.3 1.57 1.8 V Self-biased; enables ac coupling 6
Input common-mode range, VCMR VCMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled 6
CLK input resistance 3.9 4.7 5.7 kΩ Self-biased 6
LVPECL output frequency, maximum 2950 MHz Using direct to output; see Figure 25 for peak-to-peak differential amplitude 6
LVPECL output differential voltage (VOD) VOD 550 790 980 mV VOH − VOL per leg, default amplitude setting, driver not toggling 6
LVDS output differential voltage (VOD) VOD 247 360 454 mV Differential 100 Ω termination at 3.5 mA; default amplitude, driver not toggling 6
LVDS output offset voltage (VOS) VOS 1.125 1.24 1.375 V (VOH + VOL)/2 across a differential pair 6
Propagation delay CLK-to-LVPECL, high frequency clock distribution tPECL 835 995 1180 ps See Figure 43 7
Propagation delay CLK-to-LVPECL, clock distribution configuration tPECL 773 933 1090 ps See Figure 45 7
Propagation delay CLK-to-LVDS tLVDS 1.4 1.8 2.1 ns Delay off on all outputs; for all divide values 7
Propagation delay CLK-to-CMOS tCMOS 1.6 2.1 2.6 ns Fine delay off; for all divide values 7
Delay adjust, shortest range, zero scale 50 315 680 ps Register 0xA1 Bits[5:0]=101111b; Register 0xA2 Bits[5:0]=000000b 7
Delay adjust, shortest range, full scale 540 880 1180 ps Register 0xA1 Bits[5:0]=101111b; Register 0xA2 Bits[5:0]=101111b 7
Delay adjust, longest range, zero scale 200 570 950 ps Register 0xA1 Bits[5:0]=000000b; Register 0xA2 Bits[5:0]=000000b 7
Delay adjust, longest range, quarter scale 1.72 2.31 2.89 ns Register 0xA1 Bits[5:0]=000000b; Register 0xA2 Bits[5:0]=001100b 7
Delay adjust, longest range, full scale 5.7 8 10.1 ns Register 0xA1 Bits[5:0]=000000b; Register 0xA2 Bits[5:0]=101111b 7
VS, VS_LVPECL to GND VS, VS_LVPECL -0.3 3.6 V To GND 16
VCP to GND VCP -0.3 5.8 V To GND 16
REFIN, REFIN to GND REFIN -0.3 V To GND; printed max is VS + 0.3 (not numeric) 16
REFIN to REFIN -3.3 3.3 V 16
RSET to GND RSET -0.3 V To GND; printed max is VS + 0.3 (not numeric) 16
CPRSET to GND CPRSET -0.3 V To GND; printed max is VS + 0.3 (not numeric) 16
CLK, CLK to GND CLK -0.3 V To GND; printed max is VS + 0.3 (not numeric) 16
CLK to CLK CLK -1.2 1.2 V 16
SCLK, SDIO, SDO, CS to GND SCLK, SDIO, SDO, CS -0.3 V To GND; printed max is VS + 0.3 (not numeric) 16
OUT0-OUT9 to GND OUTx -0.3 V To GND; printed max is VS + 0.3 (not numeric) 16
SYNC to GND SYNC -0.3 V To GND; printed max is VS + 0.3 (not numeric) 16
REFMON, STATUS, LD to GND REFMON, STATUS, LD -0.3 V To GND; printed max is VS + 0.3 (not numeric) 16
Junction temperature TJ 150 °C 16
Storage temperature range TSTG -65 150 °C 16
Lead temperature 300 °C 10 sec 16
Thermal resistance, junction-to-ambient (64-lead LFCSP) θJA 24 °C/W 4-layer board, still air, EIA/JESD51-2 16

CAD (KiCad official)

  • Symbol: AD9516-1BCPZ-REEL7
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: ad9516-1bcpz-reel7-etched.step / ad9516-1bcpz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9516-1bcpz-reel7.step / ad9516-1bcpz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (80 pp, sha256 89982384a237e496, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF