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AD9512BCPZ-REEL7

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Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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AD9512BCPZ-REEL7

Analog Devices · Clock Generators / Frequency Synthesizers / PLL · LFCSP-48(7x7)

AD9512BCPZ-REEL7 from Analog Devices, in a LFCSP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DSYNC input Detect Sync input used for multichip synchronization.
2 DSYNCB input Detect Sync Complement input used for multichip synchronization.
3 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
4 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
5 DNC unconnected Do Not Connect; leave this pin unconnected.
6 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
7 CLK2 input Clock input 2 (differential or single-ended, up to 1.6 GHz input frequency).
8 CLK2B input Complementary clock input 2, used in conjunction with CLK2 (up to 1.6 GHz input frequency).
9 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
10 CLK1 input Clock input 1 (differential or single-ended, up to 1.6 GHz input frequency).
11 CLK1B input Complementary clock input 1, used in conjunction with CLK1 (up to 1.6 GHz input frequency).
12 FUNCTION input Multipurpose input programmable as reset (RESETB), sync (SYNCB), or power-down (PDB) pin.
13 STATUS output Output used to monitor the status of multichip synchronization (low indicates in sync).
14 SCLK input Serial data clock for the serial control port, internally pulled down by a 30 kΩ resistor to ground.
15 SDIO bidirectional Serial data I/O; input only by default, or bidirectional when enabled via register 00h<7> = 1b.
16 SDO output Serial data output used for readback in unidirectional I/O mode (default).
17 CSB input Serial port chip select, active low; must not be left NC or tied low and is internally pulled down by a 30 kΩ resistor.
18 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
19 GND power_in Ground; connect to the system ground plane.
20 OUT2B output Complementary LVPECL output 2 (1.2 GHz maximum output frequency).
21 OUT2 output LVPECL output 2 (1.2 GHz maximum output frequency).
22 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
23 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
24 GND power_in Ground; connect to the system ground plane.
25 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
26 OUT1B output Complementary LVPECL output 1 (1.2 GHz maximum output frequency).
27 OUT1 output LVPECL output 1 (1.2 GHz maximum output frequency).
28 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
29 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
30 OUT4B output Complementary LVDS/inverted CMOS output 4 (LVDS 800 MHz or CMOS 250 MHz); OUT4 includes a delay block.
31 OUT4 output LVDS/CMOS output 4 (LVDS 800 MHz or CMOS 250 MHz); includes a delay block.
32 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
33 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
34 OUT3B output Complementary LVDS/inverted CMOS output 3 (LVDS 800 MHz or CMOS 250 MHz).
35 OUT3 output LVDS/CMOS output 3 (LVDS 800 MHz or CMOS 250 MHz).
36 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
37 GND power_in Ground; connect to the system ground plane.
38 GND power_in Ground; connect to the system ground plane.
39 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
40 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
41 OUT0B output Complementary LVPECL output 0 (1.2 GHz maximum output frequency).
42 OUT0 output LVPECL output 0 (1.2 GHz maximum output frequency).
43 GND power_in Ground; connect to the system ground plane.
44 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
45 RSET passive Current set resistor to ground; nominal value 4.12 kΩ.
46 GND power_in Ground; connect to the system ground plane.
47 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
48 VS power_in Power supply, 3.3 V nominal (VS = 3.3 V ±5%; absolute maximum -0.3 V to +3.6 V with respect to GND).
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-48(7x7)
Category RTC/Clock Chip
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage tolerance VS -5 5 % 3.3 V ± 5% supply 43
Ambient operating temperature TA -40 85 °C Min/Max over full VS and TA variation 4
Supply voltage absolute maximum VS -0.3 3.6 V With respect to GND 16
CLK1 to CLK1B differential absolute maximum -1.2 1.2 V CLK1 with respect to CLK1B 16
CLK2 to CLK2B differential absolute maximum -1.2 1.2 V CLK2 with respect to CLK2B 16
Junction temperature TJ 150 °C 16
Storage temperature TSTG -65 150 °C 16
Lead temperature 300 °C 10 sec 16
Thermal resistance junction to ambient θJA 28.5 °C/W 48-lead LFCSP, 4-layer board in still air, EIA/JESD51-7 16
Input frequency 0 1.6 GHz CLK1, CLK2 clock inputs 4
Input sensitivity 150 mV p-p Jitter performance can be improved with higher slew rates 4
Input common-mode voltage VCM 1.5 1.6 1.7 V Self-biased; enables ac coupling 4
Input common-mode range VCMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled 4
Input resistance 4 4.8 5.6 kΩ Self-biased 4
LVPECL differential output voltage VOD 660 810 965 mV Termination = 50 Ω to VS − 2 V; output level 3Dh (3Eh) (3Fh)<3:2> = 10b 4
LVDS differential output voltage VOD 250 360 450 mV Termination = 100 Ω differential; default output level 40h (41h)<2:1> = 01b; 3.5 mA termination current 4
LVDS output offset voltage VOS 1.125 1.23 1.375 V Termination = 100 Ω differential; 3.5 mA termination current 4
LVDS short-circuit current ISA, ISB 14 24 mA Output shorted to GND 4
LVPECL output rise time tRP 130 180 ps 20% to 80%, measured differentially 5
LVPECL output fall time tFP 130 180 ps 80% to 20%, measured differentially 5
LVDS output rise time tRL 200 350 ps 20% to 80%, measured differentially 5
LVDS output fall time tFL 210 350 ps 80% to 20%, measured differentially 5
CMOS output rise time tRC 681 865 ps 20% to 80%; CLOAD = 3 pF 5
CMOS output fall time tFC 646 992 ps 80% to 20%; CLOAD = 3 pF 5
LVPECL propagation delay, divide bypass tPECL 335 490 635 ps CLK-to-LVPECL OUT, divide = bypass 5
LVPECL propagation delay, divide 2 to 32 tPECL 375 545 695 ps CLK-to-LVPECL OUT, divide = 2 − 32 5
LVDS propagation delay, divide bypass tLVDS 0.99 1.33 1.59 ns CLK-to-LVDS OUT, delay off on OUT4, divide = bypass 5
LVDS propagation delay, divide 2 to 32 tLVDS 1.04 1.38 1.64 ns CLK-to-LVDS OUT, delay off on OUT4, divide = 2 − 32 5
CMOS propagation delay, divide bypass tCMOS 1.02 1.39 1.71 ns CLK-to-CMOS OUT, delay off on OUT4, divide = bypass 5
CMOS propagation delay, divide 2 to 32 tCMOS 1.07 1.44 1.76 ns CLK-to-CMOS OUT, delay off on OUT4, divide = 2 − 32 5
Output skew OUT1 to OUT0 (LVPECL) tSKP2 70 100 140 ps Same part 5
Delay adjust shortest range zero scale 0.05 0.36 0.68 ns OUT4 shortest delay range, 36h<5:1> 00000b 6
Delay adjust shortest range full scale 0.72 1.12 1.51 ns OUT4 shortest delay range, 36h<5:1> 11111b 6
Delay adjust longest range zero scale 0.2 0.57 0.95 ns OUT4 longest delay range, 36h<5:1> 00000b 6
Delay adjust longest range full scale 9 10.2 11.6 ns OUT4 longest delay range, 36h<5:1> 11111b 6
Serial port input logic 1 voltage 2 V CSB, SCLK, SDIO inputs 12
Serial port input logic 0 voltage 0.8 V CSB, SCLK, SDIO inputs 12
Serial port output logic 1 voltage 2.7 V SDIO, SDO outputs 12
Serial port output logic 0 voltage 0.4 V SDIO, SDO outputs 12
Serial port clock rate 1/tSCLK 25 MHz SCLK 12
Power-up default mode power dissipation 550 600 mW Power-up default state; does not include power dissipated in output load resistors; no clock 14
Full sleep power-down power 35 60 mW Maximum sleep: 0Ah<1:0> = 01b and 58h<4> = 1b; does not include power in terminations 14
Power-down (PDB) power 60 80 mW FUNCTION pin PDB operation, 58h<6:5> = 11b; PDB pulled low; does not include power in terminations 14

CAD (KiCad official)

  • Symbol: AD9512BCPZ-REEL7
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: LFCSP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ad9512bcpz-reel7-etched.step / ad9512bcpz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9512bcpz-reel7.step / ad9512bcpz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (48 pp, sha256 d1b41ee2be9937bf, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF