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AD9257BCPZ-40

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Analog Devices Analog To Digital Converters (ADC), LFCSP-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitionad9257bcpz-40factory-2.0.0extractor-text

Verified AD9257BCPZ-40

by Ray · last 30 Oct 2026 · 1 record · files match
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Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
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  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD9257BCPZ-40 · LFCSP-64(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 38-page datasheet
  • ✓distributor: lcsc C578834, digikey 505-AD9257BCPZ-40-ND, mouser 584-AD9257BCPZ-40
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-3fkhifan/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad9257bcpz-40.kicad_sym✓ ad9257bcpz-40.kicad_mod✓ ad9257bcpz-40.step
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Contents

README

markdown

AD9257BCPZ-40

Analog Devices · Analog To Digital Converters (ADC) · LFCSP-64(9x9)

AD9257BCPZ-40 from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD power_in 1.8 V analog supply.
2 VIN+ G power_in ADC G analog input true.
3 VIN- G power_in ADC G analog input complement.
4 AVDD power_in 1.8 V analog supply.
5 VIN- H power_in ADC H analog input complement.
6 VIN+ H power_in ADC H analog input true.
7 AVDD power_in 1.8 V analog supply.
8 AVDD power_in 1.8 V analog supply.
9 CLK- input Input clock complement; accepts LVPECL, CMOS or LVDS sample clock.
10 CLK+ input Input clock true; accepts LVPECL, CMOS or LVDS sample clock.
11 AVDD power_in 1.8 V analog supply.
12 AVDD power_in 1.8 V analog supply.
13 DNC unconnected Do not connect; do not connect to this pin.
14 DRVDD power_in 1.8 V digital output driver supply.
15 D- H output ADC H digital output complement (LVDS serial data).
16 D+ H output ADC H digital output true (LVDS serial data).
17 D- G output ADC G digital output complement (LVDS serial data).
18 D+ G output ADC G digital output true (LVDS serial data).
19 D- F output ADC F digital output complement (LVDS serial data).
20 D+ F output ADC F digital output true (LVDS serial data).
21 D- E output ADC E digital output complement (LVDS serial data).
22 D+ E output ADC E digital output true (LVDS serial data).
23 DCO- output Data clock output complement used for capturing data on the outputs.
24 DCO+ output Data clock output true used for capturing data on the outputs.
25 FCO- output Frame clock output complement signaling a new output byte.
26 FCO+ output Frame clock output true signaling a new output byte.
27 D- D output ADC D digital output complement (LVDS serial data).
28 D+ D output ADC D digital output true (LVDS serial data).
29 D- C output ADC C digital output complement (LVDS serial data).
30 D+ C output ADC C digital output true (LVDS serial data).
31 D- B output ADC B digital output complement (LVDS serial data).
32 D+ B output ADC B digital output true (LVDS serial data).
33 D- A output ADC A digital output complement (LVDS serial data).
34 D+ A output ADC A digital output true (LVDS serial data).
35 DRVDD power_in 1.8 V digital output driver supply.
36 DNC unconnected Do not connect; do not connect to this pin.
37 AVDD power_in 1.8 V analog supply.
38 SCLK/DTP input SPI serial clock, or digital test pattern control when SPI is not used.
39 SDIO/DFS bidirectional SPI serial data input/output, or data format select when SPI is not used.
40 CSB input SPI chip select bar, active low; tie to AVDD to disable the serial port.
41 PDWN input Power-down control pin.
42 AVDD power_in 1.8 V analog supply.
43 VIN+ A power_in ADC A analog input true.
44 VIN- A power_in ADC A analog input complement.
45 AVDD power_in 1.8 V analog supply.
46 VIN- B power_in ADC B analog input complement.
47 VIN+ B power_in ADC B analog input true.
48 AVDD power_in 1.8 V analog supply.
49 VIN+ C power_in ADC C analog input true.
50 VIN- C power_in ADC C analog input complement.
51 AVDD power_in 1.8 V analog supply.
52 VIN- D power_in ADC D analog input complement.
53 VIN+ D power_in ADC D analog input true.
54 RBIAS passive Sets analog current bias; connect to a 10 kΩ (1% tolerance) resistor to ground.
55 SENSE input Reference mode selection.
56 VREF power_in Voltage reference input/output.
57 VCM output Analog output voltage at midsupply that sets the common mode of the analog inputs.
58 SYNC input Digital input to the clock divider with a 30 kΩ internal pull-down.
59 AVDD power_in 1.8 V analog supply.
60 VIN+ E power_in ADC E analog input true.
61 VIN- E power_in ADC E analog input complement.
62 AVDD power_in 1.8 V analog supply.
63 VIN- F power_in ADC F analog input complement.
64 VIN+ F power_in ADC F analog input true.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-64(9x9)
Category Data Acquisition
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Offset Error -0.6 -0.3 0.1 % FSR Full 3
Offset Matching 0 0.2 0.6 % FSR Full 3
Gain Error -6 -2.1 2 % FSR Full 3
Gain Matching -1 1.7 5 % FSR Full 3
Differential Nonlinearity (DNL) DNL -1 1.7 LSB Full; typ printed as -0.5/+0.8 3
Integral Nonlinearity (INL) INL -3.1 1.1 3.1 LSB Full 3
Offset Error Temperature Drift -2 2 ppm/°C Full 3
Internal Voltage Reference Output Voltage (1 V Mode) VREF 0.98 0.99 1.01 V Full 3
Load Regulation at 1.0 mA (VREF = 1 V) 2 mV Full 3
Input Resistance (VREF) 7.5 kΩ Full 3
Differential Input Voltage (VREF = 1 V) 2 V p-p Full 3
Common-Mode Voltage 0.9 V Full 3
Common-Mode Range 0.5 1.3 V Full 3
Differential Input Resistance 5.2 kΩ 3
Differential Input Capacitance 3.5 pF Full 3
AVDD Supply Voltage AVDD 1.7 1.8 1.9 V Full 3
DRVDD Supply Voltage DRVDD 1.7 1.8 1.9 V Full 3
Power-Down Dissipation 1 mW 25°C 3
Signal-to-Noise Ratio (SNR) fIN = 19.7 MHz SNR 73.5 75.8 dBFS fIN = 19.7 MHz, Full 4
Signal-to-Noise and Distortion (SINAD) fIN = 19.7 MHz SINAD 72.5 75.7 dBFS fIN = 19.7 MHz, Full 4
Effective Number of Bits (ENOB) fIN = 19.7 MHz ENOB 11.7 12.3 Bits fIN = 19.7 MHz, Full 4
Spurious-Free Dynamic Range (SFDR) fIN = 19.7 MHz SFDR 80 96 dBc fIN = 19.7 MHz, Full 4
Crosstalk -100 dB 25°C, 10 MHz analog input on one channel 5
Power Supply Rejection Ratio AVDD PSRR 52 dB 25°C 5
Power Supply Rejection Ratio DRVDD PSRR 73 dB 25°C 5
Analog Input Bandwidth, Full Power 650 MHz 25°C 5
Clock Differential Input Voltage 0.2 3.6 V p-p Full 5
Clock Input Common-Mode Voltage 0.9 V Full 5
Clock Input Resistance (Differential) 15 kΩ 25°C 5
Clock Input Capacitance 4 pF 25°C 5
Logic 1 Voltage (PDWN, SYNC, SCLK) 1.2 V Full 5
Logic 0 Voltage (PDWN, SYNC, SCLK) 0 0.8 V Full 5
Input Resistance (PDWN, SYNC, SCLK) 30 kΩ 25°C 5
Logic 1 Voltage (CSB) 1.2 V Full 5
Logic 0 Voltage (CSB) 0 0.8 V Full 5
Input Resistance (CSB) 26 kΩ 25°C 5
Logic 1 Voltage (SDIO input) 1.2 V Full 5
Logic 0 Voltage (SDIO input) 0 0.8 V Full 5
Input Resistance (SDIO) 26 kΩ 25°C 5
Logic 1 Voltage (SDIO output) 1.79 V IOH = 800 μA, Full 5
Logic 0 Voltage (SDIO output) 0.05 V IOL = 50 μA, Full 5
AVDD to AGND AVDD -0.3 2 V 9
DRVDD to AGND DRVDD -0.3 2 V 9
Digital Outputs to AGND -0.3 2 V D±x, DCO±, FCO± to AGND 9
CLK+, CLK− to AGND -0.3 2 V 9
VIN+x, VIN−x to AGND -0.3 2 V 9
SCLK/DTP, SDIO/DFS, CSB to AGND -0.3 2 V 9
SYNC, PDWN to AGND -0.3 2 V 9
RBIAS to AGND -0.3 2 V 9
VREF, SENSE to AGND -0.3 2 V 9
Operating Temperature Range (Ambient) -40 85 °C Ambient 9
Maximum Junction Temperature 150 °C 9
Lead Temperature (Soldering) 300 °C 10 sec 9
Storage Temperature Range (Ambient) -65 150 °C Ambient 9
Thermal Resistance θJA θJA 22.3 °C/W 0 m/s airflow, JEDEC 51-7 2S2P 9
Thermal Resistance θJA θJA 19.5 °C/W 1.0 m/s airflow 9
Thermal Resistance θJA θJA 17.5 °C/W 2.5 m/s airflow 9
Thermal Resistance θJC θJC 1.4 °C/W 9
Thermal Characteristic ΨJT ΨJT 0.1 °C/W 0 m/s airflow 9
Thermal Characteristic ΨJT ΨJT 0.2 °C/W 1.0 m/s airflow 9

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper Pin 0. The copper plane should have several vias to achieve the 37

CAD (KiCad official)

  • Symbol: AD9257BCPZ-40
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: ad9257bcpz-40-etched.step / ad9257bcpz-40-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9257bcpz-40.step / ad9257bcpz-40.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (38 pp, sha256 2faa91212f13cdb5, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF