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AD9245BCPZ-80

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Analog Devices Analog To Digital Converters (ADCs), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersad9245bcpz-80factory-2.0.0extractor-text

Verified AD9245BCPZ-80

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD9245BCPZ-80 · LFCSP-32(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 32-page datasheet
  • ✓distributor: lcsc C578827, digikey 505-AD9245BCPZ-80-ND, mouser 584-AD9245BCPZ-80
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-884yl42i/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad9245bcpz-80.kicad_sym✓ ad9245bcpz-80.kicad_mod✓ ad9245bcpz-80.step
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AD9245BCPZ-80

Analog Devices · Analog To Digital Converters (ADCs) · LFCSP-32(5x5)

AD9245BCPZ-80 from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DNC unconnected Do Not Connect; this pin must not be connected to anything.
2 CLK input Single-ended clock input that controls all internal conversion cycles.
3 DNC unconnected Do Not Connect; this pin must not be connected to anything.
4 PDWN input Power-down function select input for the converter.
5 D0 output Data output bit D0 (LSB), driven from DRVDD logic levels (2.5 V or 3.3 V logic families).
6 D1 output Data output bit D1, driven from DRVDD logic levels (2.5 V or 3.3 V logic families).
7 D2 output Data output bit D2, driven from DRVDD logic levels (2.5 V or 3.3 V logic families).
8 D3 output Data output bit D3, driven from DRVDD logic levels (2.5 V or 3.3 V logic families).
9 D4 output Data output bit D4, driven from DRVDD logic levels (2.5 V or 3.3 V logic families).
10 D5 output Data output bit D5, driven from DRVDD logic levels (2.5 V or 3.3 V logic families).
11 D6 output Data output bit D6, driven from DRVDD logic levels (2.5 V or 3.3 V logic families).
12 D7 output Data output bit D7, driven from DRVDD logic levels (2.5 V or 3.3 V logic families).
13 D8 output Data output bit D8, driven from DRVDD logic levels (2.5 V or 3.3 V logic families).
14 D9 output Data output bit D9, driven from DRVDD logic levels (2.5 V or 3.3 V logic families).
15 DGND power_in Digital output ground; return path for the output driver supply DRVDD.
16 DRVDD power_in Digital output driver supply, 2.25 V to 3.6 V (3.0 V typical) per the DC specifications.
17 D10 output Data output bit D10, driven from DRVDD logic levels (2.5 V or 3.3 V logic families).
18 D11 output Data output bit D11, driven from DRVDD logic levels (2.5 V or 3.3 V logic families).
19 D12 output Data output bit D12, driven from DRVDD logic levels (2.5 V or 3.3 V logic families).
20 D13 output Data output bit D13 (MSB), driven from DRVDD logic levels (2.5 V or 3.3 V logic families).
21 OTR output Out-of-range indicator that signals an overflow condition when the input is beyond the selected input range.
22 MODE input Data format select and DCS mode selection pin; selects offset binary or twos complement output and the clock duty-cycle stabilizer mode (see Table 11).
23 SENSE input Reference mode selection pin that configures internal or external reference operation (see Table 10).
24 VREF power_in Voltage reference input/output pin for the on-chip reference.
25 REFB passive Differential reference negative (-) terminal.
26 REFT passive Differential reference positive (+) terminal.
27 AVDD power_in Analog power supply, 2.7 V to 3.6 V (3.0 V typical) per the DC specifications.
28 AGND power_in Analog ground pin.
29 VIN+ power_in Positive analog input pin of the differential input; the 1 V p-p to 2 V p-p input span is set by the reference mode.
30 VIN- power_in Negative analog input pin of the differential input; forms a differential pair with VIN+.
31 AGND power_in Analog ground pin.
32 AVDD power_in Analog power supply, 2.7 V to 3.6 V (3.0 V typical) per the DC specifications.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-32(5x5)
Category Data Converters
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Offset Error -1.2 1.2 % FSR 1.0 V internal reference 4
Gain Error -4.16 4.16 % FSR 1.0 V internal reference 4
Differential Nonlinearity (DNL) -1 1 LSB Measured at the maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit 4
Integral Nonlinearity (INL) -5.15 5.15 LSB Measured at the maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit 4
Offset Error temperature drift -10 10 ppm/°C With a 1.0 V internal reference 4
Gain Error temperature drift -12 12 ppm/°C 4
Gain Error temperature drift -17 17 ppm/°C With a 1.0 V internal reference 4
Output Voltage Error (1 V Mode) -34 34 mV 4
Load Regulation -2 2 mV @ 1.0 mA 4
Output Voltage Error (0.5 V Mode) -6 6 mV 4
Load Regulation -1 1 mV @ 0.5 mA 4
AVDD supply voltage AVDD 2.7 3 3.6 V 4
DRVDD supply voltage DRVDD 2.25 2.5 3.6 V 4
Supply current IAVDD 122 138 mA 4
Power supply rejection ratio PSRR -0.01 0.01 % FSR 4
Maximum Conversion Rate 80 MSPS 8
Minimum Conversion Rate 1 MSPS 8
CLK Period 12.5 ns 8
CLK Pulse Width High 4.6 ns With duty cycle stabilizer enabled 8
CLK Pulse Width Low 4.6 ns With duty cycle stabilizer enabled 8
Output Delay (tPD) tPD 4.2 ns Measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output 8
Pipeline Delay (Latency) 7 Cycles 8
Aperture Delay tA 1 ns 8
Aperture Uncertainty Jitter tJ 0.3 ps rms 8
Wake-Up Time 7 ms With 0.1 μF and 10 μF capacitors on REFT and REFB 8
Out-of-Range Recovery Time 2 Cycles 8
AVDD to AGND AVDD -0.3 3.9 V With respect to AGND 9
DRVDD to DGND DRVDD -0.3 3.9 V With respect to DGND 9
AGND to DGND -0.3 0.3 V With respect to DGND 9
AVDD to DRVDD -3.9 3.9 V With respect to DRVDD 9
Storage Temperature Range -65 125 °C 9
Operating Temperature Range -40 85 °C 9
Lead Temperature 300 °C Soldering 10 sec 9
Junction Temperature 150 °C 9
Thermal resistance junction-to-ambient θJA 32.5 °C/W 32-Lead LFCSP, 4-layer board in still air per EIA/JESD51-1 9
Thermal resistance junction-to-case θJC 32.71 °C/W 32-Lead LFCSP 9

CAD (KiCad official)

  • Symbol: AD9245BCPZ-80
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: ad9245bcpz-80-etched.step / ad9245bcpz-80-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9245bcpz-80.step / ad9245bcpz-80.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (32 pp, sha256 8fa61d01efdba4ad, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF