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AD9238BCPZ-20

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Analog Devices Analog To Digital Converters (ADCs), LFCSP-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad9238bcpz-20factory-2.0.0extractor-text

Verified AD9238BCPZ-20

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD9238BCPZ-20 · LFCSP-64(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 46-page datasheet
  • ✓distributor: lcsc C653340, digikey AD9238BCPZ-20-ND, mouser 584-AD9238BCPZ-20
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-wo69qm4k/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.45)
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad9238bcpz-20.kicad_sym✓ ad9238bcpz-20.kicad_mod✓ ad9238bcpz-20.step
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Contents

README

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AD9238BCPZ-20

Analog Devices · Analog To Digital Converters (ADCs) · LFCSP-64(9x9)

AD9238BCPZ-20 from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground.
2 VIN+_A power_in Analog input pin (+) for Channel A.
3 VIN-_A power_in Analog input pin (-) for Channel A.
4 AGND power_in Analog ground.
5 AVDD power_in Analog power supply (2.7 V to 3.6 V).
6 REFT_A passive Differential reference (+) for Channel A.
7 REFB_A passive Differential reference (-) for Channel A.
8 VREF power_in Voltage reference input/output.
9 SENSE input Reference mode selection.
10 REFB_B passive Differential reference (-) for Channel B.
11 REFT_B passive Differential reference (+) for Channel B.
12 AVDD power_in Analog power supply (2.7 V to 3.6 V).
13 AGND power_in Analog ground.
14 VIN-_B power_in Analog input pin (-) for Channel B.
15 VIN+_B power_in Analog input pin (+) for Channel B.
16 AGND power_in Analog ground.
17 AVDD power_in Analog power supply (2.7 V to 3.6 V).
18 CLK_B input Clock input pin for Channel B.
19 DCS input Enables duty cycle stabilizer (DCS) mode when tied high.
20 DFS input Data output format select: low for offset binary, high for twos complement.
21 PDWN_B input Power-down for Channel B: logic 0 enables, logic 1 powers down (outputs static, not High-Z).
22 OEB_B input Output enable for Channel B: logic 0 enables Data Bus B, logic 1 sets outputs to High-Z.
23 DNC unconnected Do not connect; should be left floating.
24 DNC unconnected Do not connect; should be left floating.
25 D0_B output Channel B data output bit 0 (LSB).
26 D1_B output Channel B data output bit 1.
27 D2_B output Channel B data output bit 2.
28 DRGND power_in Digital output ground.
29 DRVDD power_in Digital output driver supply; decouple to DRGND with at least 0.1 µF (recommended 0.1 µF in parallel with 10 µF).
30 D3_B output Channel B data output bit 3.
31 D4_B output Channel B data output bit 4.
32 D5_B output Channel B data output bit 5.
33 D6_B output Channel B data output bit 6.
34 D7_B output Channel B data output bit 7.
35 D8_B output Channel B data output bit 8.
36 D9_B output Channel B data output bit 9.
37 D10_B output Channel B data output bit 10.
38 D11_B output Channel B data output bit 11 (MSB).
39 OTR_B output Out-of-range indicator for Channel B.
40 DRGND power_in Digital output ground.
41 DRVDD power_in Digital output driver supply; decouple to DRGND with at least 0.1 µF (recommended 0.1 µF in parallel with 10 µF).
42 DNC unconnected Do not connect; should be left floating.
43 DNC unconnected Do not connect; should be left floating.
44 D0_A output Channel A data output bit 0 (LSB).
45 D1_A output Channel A data output bit 1.
46 D2_A output Channel A data output bit 2.
47 D3_A output Channel A data output bit 3.
48 D4_A output Channel A data output bit 4.
49 D5_A output Channel A data output bit 5.
50 D6_A output Channel A data output bit 6.
51 D7_A output Channel A data output bit 7.
52 DRVDD power_in Digital output driver supply; decouple to DRGND with at least 0.1 µF (recommended 0.1 µF in parallel with 10 µF).
53 DRGND power_in Digital output ground.
54 D8_A output Channel A data output bit 8.
55 D9_A output Channel A data output bit 9.
56 D10_A output Channel A data output bit 10.
57 D11_A output Channel A data output bit 11 (MSB).
58 OTR_A output Out-of-range indicator for Channel A.
59 OEB_A input Output enable for Channel A: logic 0 enables Data Bus A, logic 1 sets outputs to High-Z.
60 PDWN_A input Power-down for Channel A: logic 0 enables, logic 1 powers down (outputs static, not High-Z).
61 MUX_SELECT input Data multiplexed mode select; high setting disables output data multiplexed mode.
62 SHARED_REF input Shared reference control: low for independent reference mode, high for shared reference mode.
63 CLK_A input Clock input pin for Channel A.
64 AVDD power_in Analog power supply (2.7 V to 3.6 V).
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-64(9x9)
Category ADC/DAC/Data Conversion
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Offset Error -1.2 0.3 1.2 % FSR Full; typ printed ±0.30 4
Gain Error -2.2 0.3 2.2 % FSR Full; typ printed ±0.30 4
Differential Nonlinearity (DNL) DNL -0.9 0.35 0.9 LSB 25°C; typ printed ±0.35 4
Integral Nonlinearity (INL) INL -1.4 0.4 1.4 LSB 25°C; typ printed ±0.40 4
Output Voltage Error (1 V Mode) -35 5 35 mV Full; typ printed ±5 4
AVDD Supply Voltage AVDD 2.7 3 3.6 V Full 4
DRVDD Supply Voltage DRVDD 2.25 3 3.6 V Full 4
Sine Wave Input Power Consumption 190 212 mW Full 4
High Level Input Voltage 2 V Full 6
Low Level Input Voltage 0.8 V Full 6
High Level Input Current -10 10 µA Full 6
Low Level Input Current -10 10 µA Full 6
Low Level Output Voltage 0.05 V Full 6
Output Delay tPD 2 3.5 6 ns Full 6
No Missing Codes Guaranteed 12 Bits Full 4
Resolution 12 Bits Full 4
Offset Error Temperature Drift 4 µV/°C Full 4
Gain Error Temperature Drift 12 ppm/°C Full 4
Input Capacitance (analog) 7 pF Full 4
Reference Input Resistance 7 kΩ Full 4
IAVDD Supply Current IAVDD 60 mA Full 4
IDRVDD Supply Current IDRVDD 4 mA Full 4
DC Input Power Consumption 180 mW Full 4
Standby Power 2 mW Full 4
Crosstalk -85 dB Full 5
Maximum Conversion Rate 20 MSPS Full 6
Minimum Conversion Rate 1 MSPS Full 6
CLK Period 50 ns Full 6
CLK Pulse-Width High 15 ns Full 6
CLK Pulse-Width Low 15 ns Full 6
AVDD to AGND -0.3 3.9 V 7
DRVDD to DRGND -0.3 3.9 V 7
AGND to DRGND -0.3 0.3 V 7
AVDD to DRVDD -3.9 3.9 V 7
Operating Temperature -40 85 °C 7
Junction Temperature 150 °C 7
Lead Temperature 300 °C 10 sec 7
Storage Temperature -65 150 °C 7
Thermal Resistance, 64-lead LFCSP θJA 26.4 °C/W heat slug soldered to ground plane, 4-layer board, still air 7

CAD (KiCad official)

  • Symbol: AD9238BCPZ-20
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: ad9238bcpz-20-etched.step / ad9238bcpz-20-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9238bcpz-20.step / ad9238bcpz-20.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (46 pp, sha256 8741329eaefd4143, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF