component
AD9235BCPZRL7-40
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Analog Devices Analog To Digital Converters (ADCs), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD9235BCPZRL7-40
Analog Devices · Analog To Digital Converters (ADCs) · LFCSP-32(5x5)
AD9235BCPZRL7-40 from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DNC | unconnected | Do Not Connect; leave this pin unconnected. |
| 2 | CLK | input | Single-ended clock input pin that controls all internal conversion cycles. |
| 3 | DNC | unconnected | Do Not Connect; leave this pin unconnected. |
| 4 | PDWN | input | Power-down function selection, active high. |
| 5 | DNC | unconnected | Do Not Connect; leave this pin unconnected. |
| 6 | DNC | unconnected | Do Not Connect; leave this pin unconnected. |
| 7 | D0 (LSB) | output | Data output bit 0, least significant bit of the 12-bit output word. |
| 8 | D1 | output | Data output bit 1 of the 12-bit output word. |
| 9 | D2 | output | Data output bit 2 of the 12-bit output word. |
| 10 | D3 | output | Data output bit 3 of the 12-bit output word. |
| 11 | D4 | output | Data output bit 4 of the 12-bit output word. |
| 12 | D5 | output | Data output bit 5 of the 12-bit output word. |
| 13 | D6 | output | Data output bit 6 of the 12-bit output word. |
| 14 | D7 | output | Data output bit 7 of the 12-bit output word. |
| 15 | DGND | power_in | Digital output ground; the reference for DRVDD and the digital outputs. |
| 16 | DRVDD | power_in | Digital output driver supply, 2.25 V to 3.6 V per the DC specifications; must be decoupled to DGND with a minimum 0.1 µF capacitor, with 0.1 µF in parallel with 10 µF recommended. |
| 17 | D8 | output | Data output bit 8 of the 12-bit output word. |
| 18 | D9 | output | Data output bit 9 of the 12-bit output word. |
| 19 | D10 | output | Data output bit 10 of the 12-bit output word. |
| 20 | D11 (MSB) | output | Data output bit 11, most significant bit of the 12-bit output word. |
| 21 | OTR | output | Out-of-range indicator that signals an input overflow condition. |
| 22 | MODE | input | Data format and clock duty cycle stabilizer (DCS) mode selection. |
| 23 | SENSE | input | Reference mode selection. |
| 24 | VREF | power_in | Voltage reference input/output. |
| 25 | REFB | passive | Differential reference (−) pin. |
| 26 | REFT | passive | Differential reference (+) pin. |
| 27 | AVDD | power_in | Analog power supply, 2.7 V to 3.6 V per the DC specifications. |
| 28 | AGND | power_in | Analog ground. |
| 29 | VIN+ | power_in | Analog differential input pin (+). |
| 30 | VIN- | power_in | Analog differential input pin (−). |
| 31 | AGND | power_in | Analog ground. |
| 32 | AVDD | power_in | Analog power supply, 2.7 V to 3.6 V per the DC specifications. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-32(5x5) |
| Category | Data Converters |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Offset Error | -1.2 | 0.5 | 1.2 | % FSR | Full VI | 3 | |
| Gain Error | -2.5 | 0.5 | 2.5 | % FSR | Full VI; based on ADC only with fixed 1.0 V external reference | 3 | |
| Differential Nonlinearity (DNL) | -0.75 | 0.35 | 0.75 | LSB | Full IV | 3 | |
| Differential Nonlinearity (DNL) at 25°C | -0.35 | 0.35 | LSB | 25°C | 3 | ||
| Integral Nonlinearity (INL) | -0.9 | 0.5 | 0.9 | LSB | Full IV | 3 | |
| Integral Nonlinearity (INL) at 25°C | -0.4 | 0.4 | LSB | 25°C | 3 | ||
| Offset Error Temperature Drift | -2 | 2 | ppm/°C | 3 | |||
| Gain Error Temperature Drift | -12 | 12 | ppm/°C | 3 | |||
| Output Voltage Error (1 V Mode) | -35 | 5 | 35 | mV | 1 V mode; Full VI | 3 | |
| Output Voltage Error (0.5 V Mode) | -2.5 | 2.5 | mV | 0.5 V mode; Full V | 3 | ||
| AVDD Supply Voltage | AVDD | 2.7 | 3 | 3.6 | V | Full IV | 3 |
| DRVDD Supply Voltage | DRVDD | 2.25 | 3 | 3.6 | V | Full IV | 3 |
| Analog Supply Current | IAVDD | 30 | 55 | 100 | mA | Full V | 3 |
| Digital Supply Current | IDRVDD | 2 | 5 | 7 | mA | Full V | 3 |
| Power Supply Rejection Ratio | PSRR | -0.01 | 0.01 | % FSR | Full V | 3 | |
| Power Consumption, DC Input | 90 | 165 | 300 | mW | DC input, Full V | 3 | |
| Power Consumption, Sine Wave Input | 180 | 205 | mW | Sine wave input, Full VI | 3 | ||
| High Level Input Voltage | 2 | V | Full IV | 4 | |||
| Low Level Input Voltage | 0.8 | V | Full IV | 4 | |||
| High Level Input Current | -10 | 10 | µA | Full IV | 4 | ||
| Low Level Input Current | -10 | 10 | µA | Full IV | 4 | ||
| High-Level Output Voltage | 3.29 | V | DRVDD = 3.3 V; IOH = 50 µA; Full IV | 4 | |||
| High-Level Output Voltage | 3.25 | V | DRVDD = 3.3 V; IOH = 0.5 mA; Full IV | 4 | |||
| Low-Level Output Voltage | 0.2 | V | DRVDD = 3.3 V; IOL = 1.6 mA; Full IV | 4 | |||
| Low-Level Output Voltage | 0.05 | V | DRVDD = 3.3 V; IOL = 50 µA; Full IV | 4 | |||
| High-Level Output Voltage | 2.49 | V | DRVDD = 2.5 V; IOH = 50 µA; Full IV | 4 | |||
| High-Level Output Voltage | 2.45 | V | DRVDD = 2.5 V; IOH = 0.5 mA; Full IV | 4 | |||
| Maximum Conversion Rate | 40 | MSPS | Full VI | 4 | |||
| Minimum Conversion Rate | 1 | MSPS | Full V | 4 | |||
| CLK Pulse-Width High | 8.8 | ns | Full V | 4 | |||
| CLK Pulse-Width Low | 8.8 | ns | Full V | 4 | |||
| Spurious-Free Dynamic Range at fINPUT = 9.7 MHz | 80 | dBc | fINPUT = 9.7 MHz; Full IV | 6 | |||
| Spurious-Free Dynamic Range at fINPUT = 19.6 MHz | 80 | dBc | fINPUT = 19.6 MHz; Full IV | 6 | |||
| Spurious-Free Dynamic Range at fINPUT = 32.5 MHz | 74 | dBc | fINPUT = 32.5 MHz; Full IV | 6 | |||
| AVDD to AGND Absolute Maximum | AVDD | -0.3 | 3.9 | V | With respect to AGND | 7 | |
| DRVDD to DGND Absolute Maximum | DRVDD | -0.3 | 3.9 | V | With respect to DGND | 7 | |
| AGND to DGND Absolute Maximum | -0.3 | 0.3 | V | AGND with respect to DGND | 7 | ||
| AVDD to DRVDD Absolute Maximum | -3.9 | 3.9 | V | AVDD with respect to DRVDD | 7 | ||
| Operating Temperature | -40 | 85 | °C | 7 | |||
| Junction Temperature | 150 | °C | 7 | ||||
| Lead Temperature | 300 | °C | 10 sec | 7 | |||
| Storage Temperature | -65 | 150 | °C | 7 | |||
| Thermal Resistance Junction-to-Ambient (32-lead LFCSP) | θJA | 32.5 | °C/W | 32-lead LFCSP; 4-layer board, still air, EIA/JESD51-1 | 7 | ||
| Thermal Resistance Junction-to-Case (32-lead LFCSP) | θJC | 32.71 | °C/W | 32-lead LFCSP; 4-layer board, still air, EIA/JESD51-1 | 7 |
CAD (KiCad official)
- Symbol:
AD9235BCPZRL7-40 - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
ad9235bcpzrl7-40-etched.step/ad9235bcpzrl7-40-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad9235bcpzrl7-40.step/ad9235bcpzrl7-40.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (40 pp, sha256
88e1c7b0b3811b67, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).