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AD9224ARSZRL

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Analog Devices Analog To Digital Converters (ADCs), SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersad9224arszrlfactory-2.0.0extractor-text

Verified AD9224ARSZRL

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 28 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD9224ARSZRL · SSOP-28-208mil · 28 pins
  • ✓copper: 28 copper pads, none touching another net
  • ✓datasheet: all 28 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C114170, digikey AD9224ARSZRLTR-ND, mouser 584-AD9224ARSZR
  • ✓family: SSOP-28_5.3x10.2mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ctwwoh2i/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 28 pins = 28 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 28 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad9224arszrl.kicad_sym✓ ad9224arszrl.kicad_mod✓ ad9224arszrl.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 21h ago
viewers ad9224arszrl: viewers · Ray 21h ago
ad9224arszrl-etched.glb Publish 0.1.0 · Ray 21h ago
ad9224arszrl-etched.step ad9224arszrl: factory component page (tier=mfr) · Ray 21h ago
ad9224arszrl-hero.glb ad9224arszrl: hero GLB from the etched model (keeps the MPN mark) · Ray 21h ago
ad9224arszrl-hero.overlay.json Publish 0.1.0 · Ray 21h ago
ad9224arszrl.glb Publish 0.1.0 · Ray 21h ago
ad9224arszrl.kicad_mod Publish 0.1.0 · Ray 21h ago
ad9224arszrl.kicad_sym Publish 0.1.0 · Ray 21h ago
ad9224arszrl.lbr Publish 0.1.0 · Ray 21h ago
ad9224arszrl.step Publish 0.1.0 · Ray 21h ago
package.json Publish 0.1.0 · Ray 21h ago
page.json Set visibility: public · Ray 21h ago
README.md Publish 0.1.0 · Ray 21h ago
verification.json Verified: Published by the parts factory: tier mfr, 28 pins · Ray 19h ago

AD9224ARSZRL

Analog Devices · Analog To Digital Converters (ADCs) · SSOP-28-208mil

AD9224ARSZRL from Analog Devices, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLK input A single clock input controls all internal conversion cycles, with absolute maximum range AVSS -0.3 V to AVDD + 0.3 V.
2 BIT 12 output Least significant data output bit (LSB) of the straight binary output word.
3 BIT 11 output Data output bit 11 of the straight binary output word.
4 BIT 10 output Data output bit 10 of the straight binary output word.
5 BIT 9 output Data output bit 9 of the straight binary output word.
6 BIT 8 output Data output bit 8 of the straight binary output word.
7 BIT 7 output Data output bit 7 of the straight binary output word.
8 BIT 6 output Data output bit 6 of the straight binary output word.
9 BIT 5 output Data output bit 5 of the straight binary output word.
10 BIT 4 output Data output bit 4 of the straight binary output word.
11 BIT 3 output Data output bit 3 of the straight binary output word.
12 BIT 2 output Data output bit 2 of the straight binary output word.
13 BIT 1 output Most significant data output bit (MSB); used with OTR to determine low or high overflow.
14 OTR output Out-of-range output indicates when the input is beyond the input range (overflow condition).
15 AVDD power_in +5 V analog supply; absolute maximum AVDD to AVSS is -0.3 V to +6.5 V.
16 AVSS power_in Analog ground; absolute maximum AVSS to DRVSS is -0.3 V to +0.3 V.
17 SENSE input Reference select pin; absolute maximum range AVSS -0.3 V to AVDD + 0.3 V.
18 VREF power_in Input span select and reference I/O; absolute maximum range AVSS -0.3 V to AVDD + 0.3 V.
19 REFCOM passive Reference common, connected to AVSS; absolute maximum range to AVSS is -0.3 V to +0.3 V.
20 CAPB passive Noise reduction pin; absolute maximum range AVSS -0.3 V to AVDD + 0.3 V.
21 CAPT passive Noise reduction pin; absolute maximum range AVSS -0.3 V to AVDD + 0.3 V.
22 CML passive Common-mode level at midsupply for the analog input.
23 VINA input Analog input pin (+); absolute maximum range AVSS -0.3 V to AVDD + 0.3 V.
24 VINB input Analog input pin (-); absolute maximum range AVSS -0.3 V to AVDD + 0.3 V.
25 AVSS power_in Analog ground; absolute maximum AVSS to DRVSS is -0.3 V to +0.3 V.
26 AVDD power_in +5 V analog supply; absolute maximum AVDD to AVSS is -0.3 V to +6.5 V.
27 DRVSS power_in Digital output driver ground; absolute maximum DRVSS to AVSS is -0.3 V to +0.3 V.
28 DRVDD power_in +3 V to +5 V digital output driver supply; absolute maximum DRVDD to DRVSS is -0.3 V to +6.5 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SSOP-28-208mil
Category Data Converters
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD with respect to AVSS -0.3 6.5 V With respect to AVSS 4
DRVDD with respect to DRVSS -0.3 6.5 V With respect to DRVSS 4
AVSS with respect to DRVSS -0.3 0.3 V With respect to DRVSS 4
AVDD with respect to DRVDD -6.5 6.5 V With respect to DRVDD 4
REFCOM with respect to AVSS -0.3 0.3 V With respect to AVSS 4
Junction Temperature 150 °C 4
Storage Temperature -65 150 °C 4
Lead Temperature 300 °C 10 sec 4
Operating Temperature Range -40 85 °C Ordering guide, AD9224ARS 4
Supply Voltage AVDD AVDD 4.75 5 5.25 V ±5% AVDD Operating 2
Supply Voltage DRVDD DRVDD 2.85 5.25 V ±5% DRVDD Operating 2
Integral Nonlinearity (INL) 1.5 2.5 LSB 2
Differential Nonlinearity (DNL) 0.33 1 LSB 2
Zero Error (@ +25°C) 0.12 0.3 % FSR @ +25°C 2
Gain Error (@ +25°C), includes internal reference error 0.3 2.2 % FSR @ +25°C, includes internal voltage reference error (note 1) 2
Gain Error (@ +25°C), excludes internal reference error 0.4 1.6 % FSR @ +25°C, excludes internal voltage reference error (note 2) 2
Zero Error Temperature Drift -2 2 ppm/°C 2
Gain Error Temperature Drift (note 1) -26 26 ppm/°C 2
Gain Error Temperature Drift (note 2) -0.4 0.4 ppm/°C 2
Power Supply Rejection AVDD 0.07 0.24 % FSR AVDD (+5 V ± 0.25 V) 2
Output Voltage Tolerance (1 V Mode) 5 17 mV 2
Output Voltage Tolerance (2.0 V Mode) 10 35 mV 2
Load Regulation 1 3.4 mV Load regulation with 1 mA load current (note 3) 2
Supply Current IAVDD IAVDD 82 87 mA 2 V Internal VREF 2
Supply Current IDRVDD IDRVDD 4.3 5 mA 2 V Internal VREF 2
Power Consumption (1 V Internal Ref) 415 445 mW 1 V Internal Ref 2
Power Consumption (2 V Internal Ref) 425 450 mW 2 V Internal Ref 2
High Level Input Voltage VIH 3.5 V 3
Low Level Input Voltage VIL 1 V 3
High Level Input Current IIH -10 10 µA VIN = DRVDD 3
Low Level Input Current IIL -10 10 µA VIN = 0 V 3
High Level Output Voltage (DRVDD = 5 V) VOH 4.5 V IOH = 50 µA, DRVDD = 5 V 3
High Level Output Voltage (DRVDD = 5 V) VOH 2.4 V IOH = 0.5 mA, DRVDD = 5 V 3
Low Level Output Voltage (DRVDD = 5 V) VOL 0.4 V IOL = 1.6 mA, DRVDD = 5 V 3
Low Level Output Voltage (DRVDD = 5 V) VOL 0.1 V IOL = 50 µA, DRVDD = 5 V 3
High Level Output Voltage (DRVDD = 3 V) VOH 2.95 V IOH = 50 µA, DRVDD = 3 V 3
High Level Output Voltage (DRVDD = 3 V) VOH 2.8 V IOH = 0.5 mA, DRVDD = 3 V 3
Low Level Output Voltage (DRVDD = 3 V) VOL 0.4 V IOL = 1.6 mA, DRVDD = 3 V 3
Low Level Output Voltage (DRVDD = 3 V) VOL 0.05 V IOL = 50 µA, DRVDD = 3 V 3
Clock Period tC 25 ns 3
Clock Pulsewidth High tCH 12.37 ns 3
Clock Pulsewidth Low tCL 12.37 ns 3
Output Delay tOD 13 ns CL = 20 pF 3
Input Capacitance (analog) 10 pF 2
Input Capacitance (logic) CIN 5 pF 3
Reference Input Resistance 5 kΩ 2
Pipeline Delay (Latency) 3 Clock Cycles 3

CAD (KiCad official)

  • Symbol: AD9224ARSZRL
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
  • 3D model files: ad9224arszrl-etched.step / ad9224arszrl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9224arszrl.step / ad9224arszrl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 0bedb46accf678c4, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF