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AD9220ARSZ

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Analog Devices Analog To Digital Converters (ADCs), SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD9220ARSZ

Analog Devices · Analog To Digital Converters (ADCs) · SSOP-28-208mil

AD9220ARSZ from Analog Devices, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLK input Clock Input Pin; the A/D samples the analog input on the rising edge of the clock, and the clock period may be extended to 1 ms without degradation in specified performance at 25 °C.
2 BIT 12 output Least Significant Data Bit (LSB) of the straight binary output data.
3 BIT 11 output Data output bit 11 of the straight binary output data.
4 BIT 10 output Data output bit 10 of the straight binary output data.
5 BIT 9 output Data output bit 9 of the straight binary output data.
6 BIT 8 output Data output bit 8 of the straight binary output data.
7 BIT 7 output Data output bit 7 of the straight binary output data.
8 BIT 6 output Data output bit 6 of the straight binary output data.
9 BIT 5 output Data output bit 5 of the straight binary output data.
10 BIT 4 output Data output bit 4 of the straight binary output data.
11 BIT 3 output Data output bit 3 of the straight binary output data.
12 BIT 2 output Data output bit 2 of the straight binary output data.
13 BIT 1 output Most Significant Data Bit (MSB) of the straight binary output data, used with OTR to determine low or high overflow.
14 OTR output Out of Range indicator that signals an overflow condition of the analog input.
15 AVDD power_in 5 V Analog Supply; AVDD is nominally 5 V with ±5% operating tolerance.
16 AVSS power_in Analog Ground, nominally 0 V.
17 SENSE input Reference Select pin that selects the internal reference mode (1 V or 2.5 V).
18 VREF power_in Reference I/O pin that defines the maximum input voltage to the A/D core.
19 REFCOM passive Reference Common pin for the internal voltage reference.
20 CAPB passive Noise Reduction Pin, connected to the internal noise reduction network.
21 CAPT passive Noise Reduction Pin, connected to the internal noise reduction network.
22 CML passive Common-Mode Level (Midsupply) pin, nominally AVDD/2 for optimum distortion performance.
23 VINA input Analog Input Pin (+); valid inputs must satisfy AVSS − 0.3 V to AVDD + 0.3 V.
24 VINB input Analog Input Pin (−); valid inputs must satisfy AVSS − 0.3 V to AVDD + 0.3 V.
25 AVSS power_in Analog Ground, nominally 0 V.
26 AVDD power_in 5 V Analog Supply; AVDD is nominally 5 V with ±5% operating tolerance.
27 DVSS power_in Digital Ground for the output drivers and digital logic.
28 DVDD power_in 3 V to 5 V Digital Supply for the digital output drivers.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SSOP-28-208mil
Category Data Converters
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Resolution 12 Bits 2
Max conversion rate 10 MHz 2
Integral Nonlinearity (INL) INL -1.25 1.25 LSB 2
Differential Nonlinearity (DNL) DNL -0.75 0.75 LSB 2
Zero Error (@ 25°C) -0.3 0.3 % FSR @ 25°C 2
Gain Error (@ 25°C) -1.5 1.5 % FSR @ 25°C, including internal reference 2
Gain Error (@ 25°C) -0.75 0.75 % FSR @ 25°C, excluding internal reference 2
Power supply rejection AVDD, DVDD -0.06 0.06 % FSR +5 V ± 0.25 V 2
Input Span (with VREF = 1.0 V) 2 V p-p VREF = 1.0 V 2
Input Span (with VREF = 2.5 V) 5 V p-p VREF = 2.5 V 2
Input (VINA or VINB) Range 0 V 2
Output Voltage Tolerance (1 V Mode) -14 14 mV 1 V mode 2
Output Voltage Tolerance (2.5 V Mode) -35 35 mV 2.5 V mode 2
Load Regulation 2 mV Load regulation with 1 mA load current (in addition to that required by the AD9220) 2
Supply voltage DVDD DVDD 2.7 5.25 V 2
Supply current IAVDD IAVDD 58 mA 2
Supply current IDVDD IDVDD 4 mA 2
Power consumption 310 mW 2
SINAD SINAD 68.5 dB Input Test Frequency 1 (VINA = -0.5 dBFS) 3
Effective Number of Bits (ENOBs) ENOBs 11.1 dB Input Test Frequency 1 (VINA = -0.5 dBFS) 3
Signal-to-Noise Ratio (SNR) SNR 69 dB Input Test Frequency 1 (VINA = -0.5 dBFS) 3
Total Harmonic Distortion (THD) THD -76 dB Input Test Frequency 1 (VINA = -0.5 dBFS) 3
Spurious Free Dynamic Range (SFDR) SFDR 77.5 dB Input Test Frequency 1 (VINA = -0.5 dBFS) 3
SINAD SINAD 65 dB Input Test Frequency 2 (VINA = -0.5 dBFS) 3
Effective Number of Bits (ENOBs) ENOBs 10.5 dB Input Test Frequency 2 (VINA = -0.5 dBFS) 3
Signal-to-Noise Ratio (SNR) SNR 67.5 dB Input Test Frequency 2 (VINA = -0.5 dBFS) 3
Total Harmonic Distortion (THD) THD -68 dB Input Test Frequency 2 (VINA = -0.5 dBFS) 3
Spurious Free Dynamic Range (SFDR) SFDR 69 dB Input Test Frequency 2 (VINA = -0.5 dBFS) 3
High Level Input Voltage VIH 3.5 V 3
Low Level Input Voltage VIL 1 V 3
High Level Input Current IIH -10 10 µA VIN = DVDD 3
Low Level Input Current IIL -10 10 µA VIN = 0 V 3
High Level Output Voltage VOH 4.5 V DVDD = 5 V, IOH = 50 µA 3
High Level Output Voltage VOH 2.4 V DVDD = 5 V, IOH = 0.5 mA 3
Low Level Output Voltage VOL 0.4 V DVDD = 5 V, IOL = 1.6 mA 3
Low Level Output Voltage VOL 0.1 V DVDD = 5 V, IOL = 50 µA 3
High Level Output Voltage VOH 2.95 V DVDD = 3 V, IOH = 50 µA 3
High Level Output Voltage VOH 2.8 V DVDD = 3 V, IOH = 0.5 mA 3
Low Level Output Voltage VOL 0.05 V DVDD = 3 V, IOL = 50 µA 3
Clock Period tC 100 ns TMIN to TMAX, AVDD = 5 V, DVDD = 5 V, CL = 20 pF 4
CLOCK Pulsewidth High tCH 45 ns TMIN to TMAX, AVDD = 5 V, DVDD = 5 V, CL = 20 pF 4
CLOCK Pulsewidth Low tCL 45 ns TMIN to TMAX, AVDD = 5 V, DVDD = 5 V, CL = 20 pF 4
Output Delay tOD 8 13 19 ns TMIN to TMAX, AVDD = 5 V, DVDD = 5 V, CL = 20 pF 4
AVDD with respect to AVSS AVDD -0.3 6.5 V With respect to AVSS 4
DVDD with respect to DVSS DVDD -0.3 6.5 V With respect to DVSS 4
AVSS with respect to DVSS AVSS -0.3 0.3 V With respect to DVSS 4
AVDD with respect to DVDD AVDD -6.5 6.5 V With respect to DVDD 4
REFCOM with respect to AVSS REFCOM -0.3 0.3 V With respect to AVSS 4
Junction Temperature TJ 150 °C 4
Storage Temperature -65 150 °C 4
Lead Temperature (10 sec) 300 °C 10 sec 4
Operating temperature range (AD9220ARS) -40 85 °C Ordering guide temperature range, 28-Lead SSOP RS-28 4
Input referred noise (VREF = 2.5 V) 0.09 LSB rms VREF = 2.5 V 2
Supply current IAVDD IAVDD 51 mA 2
Power consumption 254 mW 2
Input Capacitance 16 pF 2
Thermal Resistance, junction-to-ambient, 28-Lead SSOP θJA 63.3 °C/W 4
Thermal Resistance, junction-to-case, 28-Lead SSOP θJC 23 °C/W 4

CAD (KiCad official)

  • Symbol: AD9220ARSZ
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
  • 3D model files: ad9220arsz-etched.step / ad9220arsz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9220arsz.step / ad9220arsz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (32 pp, sha256 f3133a2c8d5022e7, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF