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AD9215BCPZ-65

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Analog Devices Analog To Digital Converters (ADCs), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD9215BCPZ-65

Analog Devices · Analog To Digital Converters (ADCs) · LFCSP-32(5x5)

AD9215BCPZ-65 from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DNC unconnected Do not connect; the datasheet recommends floating this pin.
2 CLK input Clock Input Pin, a single-ended clock input that controls all internal conversion cycles.
3 DNC unconnected Do not connect; the datasheet recommends floating this pin.
4 PDWN input Power-Down Function Selection (Active High).
5 DNC unconnected Do not connect; the datasheet recommends floating this pin.
6 DNC unconnected Do not connect; the datasheet recommends floating this pin.
7 DNC unconnected Do not connect; the datasheet recommends floating this pin.
8 DNC unconnected Do not connect; the datasheet recommends floating this pin.
9 D0 (LSB) output Data Output Bit 0, the least significant bit of the digital output data.
10 D1 output Data Output Bit 1 of the digital output data.
11 D2 output Data Output Bit 2 of the digital output data.
12 D3 output Data Output Bit 3 of the digital output data.
13 D4 output Data Output Bit 4 of the digital output data.
14 D5 output Data Output Bit 5 of the digital output data.
15 DRGND power_in Digital Output Ground.
16 DRVDD power_in Digital Output Driver Supply; must be decoupled to DRGND with a minimum 0.1 μF capacitor, with 0.1 μF in parallel with 10 μF recommended.
17 D6 output Data Output Bit 6 of the digital output data.
18 D7 output Data Output Bit 7 of the digital output data.
19 D8 output Data Output Bit 8 of the digital output data.
20 D9 (MSB) output Data Output Bit 9, the most significant bit of the digital output data.
21 OR output Out-of-Range Indicator, which signals when the input is beyond the selected input range.
22 MODE input Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection.
23 SENSE input Reference Mode Selection.
24 VREF power_in Voltage Reference Input/Output.
25 REFB bidirectional Differential Reference (Negative).
26 REFT bidirectional Differential Reference (Positive).
27 AVDD power_in Analog Power Supply.
28 AGND power_in Analog Ground.
29 VIN+ power_in Analog Input Pin (+) of the differential analog input.
30 VIN− power_in Analog Input Pin (-) of the differential analog input.
31 AGND power_in Analog Ground.
32 AVDD power_in Analog Power Supply.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-32(5x5)
Category Data Converters
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Offset Error -2 0.3 2 % FSR 1.0 V internal reference, Full temp range 3
Gain Error 0 1.5 4 % FSR 1.0 V internal reference, Full temp range 3
Differential Nonlinearity (DNL) DNL -1 0.5 1 LSB Full temp range 3
Integral Nonlinearity (INL) INL -1.2 0.5 1.2 LSB Full temp range 3
Output Voltage Error (1 V Mode) -35 2 35 mV 1 V mode, Full temp range 3
Supply Voltage AVDD AVDD 2.7 3 3.3 V 3
Supply Voltage DRVDD DRVDD 2.25 2.5 3.6 V 3
High Level Input Voltage VIH 2 V CLK, PDWN; Full temp range 5
Low Level Input Voltage VIL 0.8 V CLK, PDWN; Full temp range 5
High Level Input Current IIH -650 10 µA CLK, PDWN; Full temp range 5
Low Level Input Current IIL -70 10 µA CLK, PDWN; Full temp range 5
High Level Output Voltage VOH 2.45 V DRVDD = 2.5 V, 5 pF load on each output 5
Low Level Output Voltage VOL 0.05 V DRVDD = 2.5 V, 5 pF load on each output 5
Maximum Conversion Rate fS 65 MSPS Parametric test rate for AD9215BCP-65 5
Minimum Conversion Rate fS 5 MSPS 5
Output Delay tOD 2.5 4.8 6.5 ns 5 pF load on each output; CLK 50% to DATA 50% 5
AVDD to AGND AVDD -0.3 3.9 V with respect to AGND 6
DRVDD to DRGND DRVDD -0.3 3.9 V with respect to DRGND 6
AGND to DRGND AGND -0.3 0.3 V with respect to DRGND 6
AVDD to DRVDD AVDD-DRVDD -3.9 3.9 V 6
Digital Outputs -0.3 V with respect to DRGND; max DRVDD + 0.3 V 6
CLK, MODE -0.3 V with respect to AGND; max AVDD + 0.3 V 6
VIN+, VIN- VIN -0.3 V with respect to AGND; max AVDD + 0.3 V 6
VREF VREF -0.3 V with respect to AGND; max AVDD + 0.3 V 6
SENSE SENSE -0.3 V with respect to AGND; max AVDD + 0.3 V 6
REFB, REFT REFB, REFT -0.3 V with respect to AGND; max AVDD + 0.3 V 6
PDWN PDWN -0.3 V with respect to AGND; max AVDD + 0.3 V 6
Operating Temperature TA -40 85 °C 6
Junction Temperature TJ 150 °C 6
Lead Temperature 300 °C 10 sec 6
Storage Temperature TSTG -65 150 °C 6
Thermal Resistance Junction-to-Ambient θJA 32.7 °C/W 32-lead LFCSP; heat sink soldered to ground plane 6

CAD (KiCad official)

  • Symbol: AD9215BCPZ-65
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: ad9215bcpz-65-etched.step / ad9215bcpz-65-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9215bcpz-65.step / ad9215bcpz-65.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (36 pp, sha256 0ed04b03f00da597, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF