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AD9122BCPZ

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Analog Devices Digital To Analog Converters (DACs), LFCSP-72(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersad9122bcpzfactory-2.0.0extractor-text

Verified AD9122BCPZ

by Ray · last 31 Oct 2026 · 1 record · files match
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Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 73 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD9122BCPZ · LFCSP-72(10x10) · 73 pins
  • ✓copper: 73 copper pads, none touching another net
  • ✓datasheet: all 73 pin names found in the 60-page datasheet
  • ✓distributor: lcsc C468512, digikey 505-AD9122BCPZ-ND, mouser 584-AD9122BCPZ
  • ✓family: QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-hp11xc_b/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.60)
  • ✓pads: 73 pins = 73 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 73 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad9122bcpz.kicad_sym✓ ad9122bcpz.kicad_mod✓ ad9122bcpz.step
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Contents

README

markdown

AD9122BCPZ

Analog Devices · Digital To Analog Converters (DACs) · LFCSP-72(10x10)

AD9122BCPZ from Analog Devices, in a LFCSP-72(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CVDD18 power_in 1.8 V clock supply for clock receivers, clock distribution, and PLL circuitry.
2 DACCLKP input DAC clock input, positive.
3 DACCLKN input DAC clock input, negative.
4 CVSS power_in Clock supply common.
5 FRAMEP input Frame input, positive; must be tied to DVSS if not used.
6 FRAMEN input Frame input, negative; must be tied to DVDD18 if not used.
7 IRQ output Interrupt request, open-drain active-low output; connect an external pull-up to IOVDD through a 10 kΩ resistor.
8 D15P input Data bit 15 (MSB), positive.
9 D15N input Data bit 15 (MSB), negative.
10 NC unconnected No connect; do not connect to this pin.
11 IOVDD power_in Supply for serial port I/O pins, RESET, and IRQ; 1.8 V to 3.3 V can be supplied.
12 DVDD18 power_in 1.8 V digital supply for digital core and digital data ports.
13 D14P input Data bit 14, positive.
14 D14N input Data bit 14, negative.
15 D13P input Data bit 13, positive.
16 D13N input Data bit 13, negative.
17 D12P input Data bit 12, positive.
18 D12N input Data bit 12, negative.
19 D11P input Data bit 11, positive.
20 D11N input Data bit 11, negative.
21 D10P input Data bit 10, positive.
22 D10N input Data bit 10, negative.
23 D9P input Data bit 9, positive.
24 D9N input Data bit 9, negative.
25 D8P input Data bit 8, positive.
26 D8N input Data bit 8, negative.
27 DCIP input Data clock input, positive.
28 DCIN input Data clock input, negative.
29 DVDD18 power_in 1.8 V digital supply for digital core and digital data ports.
30 DVSS power_in Digital common.
31 D7P input Data bit 7, positive.
32 D7N input Data bit 7, negative.
33 D6P input Data bit 6, positive.
34 D6N input Data bit 6, negative.
35 D5P input Data bit 5, positive.
36 D5N input Data bit 5, negative.
37 D4P input Data bit 4, positive.
38 D4N input Data bit 4, negative.
39 D3P input Data bit 3, positive.
40 D3N input Data bit 3, negative.
41 D2P input Data bit 2, positive.
42 D2N input Data bit 2, negative.
43 DVDD18 power_in 1.8 V digital supply for digital core and digital data ports.
44 DVSS power_in Digital common.
45 D1P input Data bit 1, positive.
46 D1N input Data bit 1, negative.
47 D0P input Data bit 0 (LSB), positive.
48 D0N input Data bit 0 (LSB), negative.
49 DVDD18 power_in 1.8 V digital supply for digital core and digital data ports.
50 SDO output Serial port data output (CMOS levels with respect to IOVDD).
51 SDIO bidirectional Serial port data input/output (CMOS levels with respect to IOVDD).
52 SCLK input Serial port clock input (CMOS levels with respect to IOVDD), maximum 40 MHz.
53 CS input Serial port chip select, active low (CMOS levels with respect to IOVDD).
54 RESET input Reset, active low (CMOS levels with respect to IOVDD).
55 NC unconnected No connect; do not connect to this pin.
56 AVSS power_in Analog supply common.
57 AVDD33 power_in 3.3 V analog supply.
58 IOUT2P output Q DAC positive current output.
59 IOUT2N output Q DAC negative current output.
60 AVDD33 power_in 3.3 V analog supply.
61 AVSS power_in Analog supply common.
62 REFIO output Voltage reference, nominally 1.2 V output; should be decoupled to AVSS.
63 FSADJ passive Full-scale current output adjust; place a 10 kΩ resistor from this pin to AVSS.
64 AVSS power_in Analog supply common.
65 AVDD33 power_in 3.3 V analog supply.
66 IOUT1N output I DAC negative current output.
67 IOUT1P output I DAC positive current output.
68 AVDD33 power_in 3.3 V analog supply.
69 REFCLKN input PLL reference clock input, negative; secondary function as a synchronization input.
70 REFCLKP input PLL reference clock input, positive; secondary function as a synchronization input.
71 CVDD18 power_in 1.8 V clock supply for clock receivers, clock distribution, and PLL circuitry.
72 CVDD18 power_in 1.8 V clock supply for clock receivers, clock distribution, and PLL circuitry.
73 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-72(10x10)
Category Data Converters
Pins 73

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Differential Nonlinearity DNL -2.1 2.1 LSB TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA 4
Integral Nonlinearity INL -3.7 3.7 LSB 4
Offset Error -0.001 0 0.001 % FSR 4
Gain Error (with Internal Reference) -3.6 2 3.6 % FSR typ printed as ±2 4
Full-Scale Output Current IFS 8.66 19.6 31.66 mA Based on a 10 kΩ external resistor between FSADJ and AVSS 4
Output Compliance Range -1 1 V 4
Power Supply Rejection Ratio, AVDD33 PSRR -0.3 0.3 % FSR/V 4
Output Resistance (main DAC) 10 MΩ 4
Settling Time to Within ±0.5 LSB 20 ns 4
Offset Drift 0.04 ppm/°C Main DAC temperature drift 4
Gain Drift 100 ppm/°C Main DAC temperature drift 4
Reference Voltage Drift 30 ppm/°C Main DAC temperature drift 4
Internal Reference Voltage 1.2 V 4
Reference Output Resistance 5 kΩ 4
Analog Supply Voltage AVDD33 AVDD33 3.13 3.3 3.47 V 4
Analog Supply Voltage CVDD18 CVDD18 1.71 1.8 1.89 V 4
Digital Supply Voltage DVDD18 DVDD18 1.71 1.8 1.89 V 4
Digital Supply Voltage IOVDD IOVDD 1.71 1.8 3.47 V typ printed as 1.8/3.3 4
Power Consumption, 8× Mode 1135 1241 mW 8× Mode, fDAC = 800 MSPS, IF = 10 MHz, PLL Off 4
AVDD33 supply current 55 57 mA 8× Mode, fDAC = 800 MSPS, IF = 10 MHz, PLL Off 4
CVDD18 supply current 85 90 mA 8× Mode, fDAC = 800 MSPS, IF = 10 MHz, PLL Off 4
DVDD18 supply current 444 495 mA 8× Mode, fDAC = 800 MSPS, IF = 10 MHz, PLL Off 4
Power-Down Mode Power 6.5 18.8 mW Register 0x01 = 0xF0 4
Power Consumption, 2× Mode PLL Off 834 mW 2× Mode, fDAC = 491.22 MSPS, IF = 10 MHz, PLL Off 4
Power Consumption, 2× Mode PLL On 913 mW 2× Mode, fDAC = 491.22 MSPS, IF = 10 MHz, PLL On 4
Power-Up Time 260 ms 4
Operating Range -40 25 85 °C 4
Input VIN Logic High VIN 1.2 V IOVDD = 1.8 V 5
Input VIN Logic High VIN 1.6 V IOVDD = 2.5 V 5
Input VIN Logic High VIN 2 V IOVDD = 3.3 V 5
Input VIN Logic Low VIN 0.6 V IOVDD = 1.8 V 5
Input VIN Logic Low VIN 0.8 V IOVDD = 2.5 V, 3.3 V 5
Output VOUT Logic High VOUT 1.4 V IOVDD = 1.8 V 5
Output VOUT Logic High VOUT 1.8 V IOVDD = 2.5 V 5
Output VOUT Logic High VOUT 2.4 V IOVDD = 3.3 V 5
Output VOUT Logic Low VOUT 0.4 V IOVDD = 1.8 V, 2.5 V, 3.3 V 5
LVDS Input Voltage Range VIA or VIB 825 1675 mV Applies to data, DCI, and FRAME inputs 5
LVDS Input Differential Threshold VIDTH -100 100 mV Applies to data, DCI, and FRAME inputs 5
LVDS Input Differential Hysteresis VIDTHH to VIDTHL 20 mV Applies to data, DCI, and FRAME inputs 5
LVDS Receiver Differential Input Impedance RIN 80 120 Ω Applies to data, DCI, and FRAME inputs 5
DACCLK Differential Peak-to-Peak Voltage 100 500 2000 mV 5
DACCLK Common-Mode Voltage 1.25 V Self-biased input, ac-coupled 5
DACCLK Maximum Clock Rate 1230 MHz 5
REFCLK Differential Peak-to-Peak Voltage 100 500 2000 mV 5
REFCLK Common-Mode Voltage 1.25 V 5
REFCLK Frequency (PLL Mode) 15.625 600 MHz 1 GHz ≤ fVCO ≤ 2.1 GHz 5
REFCLK Frequency (SYNC Mode) 0 600 MHz See the Multichip Synchronization section for conditions 5
SCLK Maximum Clock Rate 40 MHz 5
Minimum Pulse Width High tPWH 12.5 ns 5
Minimum Pulse Width Low tPWL 12.5 ns 5
Setup Time, SDIO to SCLK tDS 1.9 ns 5
Hold Time, SDIO to SCLK tDH 0.2 ns 5
Data Valid, SDO to SCLK tDV 2.3 ns 5
Setup Time, CS to SCLK tDCSB 1.4 ns 5
AVDD33 to AVSS, EPAD, CVSS, DVSS -0.3 3.6 V 8
IOVDD to AVSS, EPAD, CVSS, DVSS -0.3 3.6 V 8
DVDD18, CVDD18 to AVSS, EPAD, CVSS, DVSS -0.3 2.1 V 8
Junction Temperature 125 °C 8
Storage Temperature Range -65 150 °C 8
Thermal Resistance θJA θJA 20.7 °C/W 72-Lead LFCSP, EPAD soldered to ground plane 8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs thermometer code (Base 1 code) of the write counter state relative to the absolute read counter being at 0. The optimum FIFO data 34

CAD (KiCad official)

  • Symbol: AD9122BCPZ
  • Footprint: Package_DFN_QFN:QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-72(10x10), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: ad9122bcpz-etched.step / ad9122bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9122bcpz.step / ad9122bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (60 pp, sha256 b82d8acff09fb215, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF