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AD9114BCPZ

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Analog Devices Digital To Analog Converters (DACs), LFCSP-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD9114BCPZ

Analog Devices · Digital To Analog Converters (DACs) · LFCSP-40(6x6)

AD9114BCPZ from Analog Devices, in a LFCSP-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DB5 input Digital data input bit 5 of the DB[5:2] group, one of the parallel DAC data inputs.
2 DB4 input Digital data input bit 4 of the DB[5:2] group, one of the parallel DAC data inputs.
3 DB3 input Digital data input bit 3 of the DB[5:2] group, one of the parallel DAC data inputs.
4 DB2 input Digital data input bit 2 of the DB[5:2] group, one of the parallel DAC data inputs.
5 DVDDIO power_in Digital I/O supply voltage input, 1.8 V to 3.3 V nominal.
6 DVSS power_in Digital common (ground) for the digital section.
7 DVDD power_out Digital core supply output at 1.8 V; strap to DVDDIO if DVDDIO is 1.8 V, otherwise bypass with a 1.0 µF capacitor and do not load it externally.
8 DB1 input Digital data input bit 1 of the parallel DAC data inputs.
9 DB0 (LSB) input Digital input for the least significant bit of the DAC data.
10 NC unconnected No connect; not connected to the chip.
11 NC unconnected No connect; not connected to the chip.
12 NC unconnected No connect; not connected to the chip.
13 NC unconnected No connect; not connected to the chip.
14 NC unconnected No connect; not connected to the chip.
15 NC unconnected No connect; not connected to the chip.
16 DCLKIO bidirectional Data input/output clock used to qualify the input data.
17 CVDD power_in Sampling clock supply voltage input, 1.8 V to 3.3 V; must be greater than or equal to DVDD.
18 CLKIN input LVCMOS sampling clock input.
19 CVSS power_in Sampling clock supply common (ground).
20 CMLQ passive Q DAC output common-mode level; leave unconnected when the internal QRCML resistor is used, otherwise connect to AVSS through a resistor (recommended 0 Ω).
21 RLQN passive Load resistor (62.5 Ω) to CMLQ; tie to QOUTN externally to use the internal load resistor.
22 QOUTN output Complementary Q DAC current output; full-scale current is sourced when all data bits are 0s.
23 QOUTP output Q DAC current output; full-scale current is sourced when all data bits are 1s.
24 RLQP passive Load resistor (62.5 Ω) to CMLQ; tie to QOUTP externally to use the internal load resistor.
25 AVSS power_in Analog common (ground) for the analog section.
26 AVDD power_in Analog supply voltage input, 1.8 V to 3.3 V.
27 RLIP passive Load resistor (62.5 Ω) to CMLI; tie to IOUTP externally to use the internal load resistor.
28 IOUTP output I DAC current output; full-scale current is sourced when all data bits are 1s.
29 IOUTN output Complementary I DAC current output; full-scale current is sourced when all data bits are 0s.
30 RLIN passive Load resistor (62.5 Ω) to CMLI; tie to IOUTN externally to use the internal load resistor.
31 CMLI passive I DAC output common-mode level; leave unconnected when the internal IRCML resistor is used, otherwise connect to AVSS through a resistor (recommended 0 Ω).
32 FSADJQ/AUXQ passive Q DAC full-scale adjust, connected to AVSS through a resistor (nominal 4 kΩ for 8 mA) when QRSET is disabled; auxiliary Q DAC output when QRSET is enabled.
33 FSADJI/AUXI passive I DAC full-scale adjust, connected to AVSS through a resistor (nominal 4 kΩ for 8 mA) when IRSET is disabled; auxiliary I DAC output when IRSET is enabled.
34 REFIO bidirectional Reference input when the internal reference is disabled; provides a 1.0 V reference output in internal mode and requires a 0.1 µF capacitor to AVSS.
35 RESET/PINMD input Logic low selects SPI mode and a pulse high resets the SPI registers; logic high selects pin mode.
36 SCLK/CLKMD input Serial port clock input (SCLK) in SPI mode; retimer clock mode control (CLKMD) in pin mode.
37 SDIO/FORMAT bidirectional Bidirectional serial data line (SDIO) in SPI mode; data format select (FORMAT) in pin mode, low for binary and high for twos complement.
38 CS/PWRDN input Active low chip select (CS) in SPI mode; power-down input (PWRDN) in pin mode, where logic high powers down the device except the SPI port.
39 DB7 (MSB) input Digital input for the most significant bit of the DAC data.
40 DB6 input Digital data input bit 6 of the parallel DAC data inputs.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-40(6x6)
Category ADC/DAC/Data Conversion
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Gain Matching -1 1 % of FSR 6
Internal Reference Voltage 0.98 1.025 1.08 V 6
Analog supply voltage AVDD AVDD 1.7 3.5 V 6
Clock supply voltage CVDD CVDD 1.7 3.5 V 6
Digital core supply voltage DVDD DVDD 1.7 1.9 V 6
Digital I/O supply voltage DVDDIO DVDDIO 1.7 3.5 V 6
Operating range -40 25 85 °C 7
DAC clock input high level VIH 2.1 3 V DAC CLOCK INPUT (CLKIN) 7
DAC clock input low level VIL 0 0.9 V DAC CLOCK INPUT (CLKIN) 7
Maximum clock rate 125 MSPS 7
Maximum clock rate SCLK 25 MHz SERIAL PERIPHERAL INTERFACE 7
Minimum pulse width high 20 ns SERIAL PERIPHERAL INTERFACE 7
Minimum pulse width low 20 ns SERIAL PERIPHERAL INTERFACE 7
Minimum SDIO setup to SCLK tDS 10 ns SERIAL PERIPHERAL INTERFACE 7
Minimum SCLK to SDIO hold tDH 5 ns SERIAL PERIPHERAL INTERFACE 7
Maximum SCLK to valid SDIO tDV 20 ns SERIAL PERIPHERAL INTERFACE 7
Minimum SCLK to invalid SDIO tDNV 5 ns SERIAL PERIPHERAL INTERFACE 7
DVDDIO = 3.3 V input high level VIH 2.1 3 V DVDDIO = 3.3 V 7
DVDDIO = 3.3 V input low level VIL 0 0.9 V DVDDIO = 3.3 V 7
DVDDIO = 1.8 V input high level VIH 1.2 1.8 V DVDDIO = 1.8 V 7
DVDDIO = 1.8 V input low level VIL 0 0.5 V DVDDIO = 1.8 V 7
AVDD, DVDDIO, CVDD to AVSS, DVSS, CVSS -0.3 3.9 V 10
DVDD to DVSS -0.3 2.1 V 10
AVSS to DVSS, CVSS -0.3 0.3 V 10
DVSS to AVSS, CVSS -0.3 0.3 V 10
CVSS to AVSS, DVSS -0.3 0.3 V 10
REFIO, FSADJQ, FSADJI, CMLQ, CMLI to AVSS -0.3 V upper limit AVDD + 0.3 V as printed 10
QOUTP, QOUTN, IOUTP, IOUTN, RLQP, RLQN, RLIP, RLIN to AVSS -1 V upper limit AVDD + 0.3 V as printed 10
DB7 (MSB) to D0 (LSB), CS, SCLK, SDIO, RESET to DVSS -0.3 V upper limit DVDDIO + 0.3 V as printed; DBn with n = 7 for AD9114 10
CLKIN to CVSS -0.3 V upper limit CVDD + 0.3 V as printed 10
Junction temperature 125 °C 10
Storage temperature range -65 150 °C 10
Thermal resistance junction-to-ambient θJA 29.8 °C/W 40-lead LFCSP, no airflow movement 10
Thermal resistance junction-to-board θJB 19 °C/W 40-lead LFCSP, no airflow movement 10
Thermal resistance junction-to-case θJC 3.4 °C/W 40-lead LFCSP, no airflow movement 10

CAD (KiCad official)

  • Symbol: AD9114BCPZ
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: LFCSP-40(6x6) (KiCad packages3D, STEP)
  • 3D model files: ad9114bcpz-etched.step / ad9114bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9114bcpz.step / ad9114bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (53 pp, sha256 6f16bae03ae84b7e, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF