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AD9106BCPZ

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ADI Others, LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD9106BCPZ

ADI · Others · LFCSP-32(5x5)

AD9106BCPZ from ADI, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCLK input SPI clock input for the serial port.
2 SDIO bidirectional Primary bidirectional data line for the SPI port.
3 DGND power_in Digital ground.
4 DLDO2 power_out 1.8 V internal digital LDO2 output; when the internal digital LDO2 is enabled, it must be bypassed with a 0.1 µF capacitor.
5 DVDD power_in 3.3 V external digital power supply that defines the logic level of the digital (SPI) interface.
6 DLDO1 power_out 1.8 V internal digital LDO1 output; when the internal digital LDO1 is enabled, it must be bypassed with a 0.1 µF capacitor.
7 SDO/SDI2/DOUT bidirectional Multifunction pin: serial data output (SDO) in 4-wire SPI mode, second SPI data input (SDI2) in double-SPI mode for SRAM writes, and programmable pulse output (DOUT) in data output mode.
8 CS input SPI port chip select, active low.
9 RESET input Active-low reset pin that resets registers to their default values.
10 IOUTP4 output DAC4 current output, positive side.
11 IOUTN4 output DAC4 current output, negative side.
12 AVDD2 power_in 1.8 V to 3.3 V power supply input for DAC3 and DAC4.
13 IOUTN3 output DAC3 current output, negative side.
14 IOUTP3 output DAC3 current output, positive side.
15 AGND power_in Analog ground.
16 FSADJ3 passive External full-scale current output adjust for DAC3.
17 FSADJ4 passive External full-scale current output adjust for DAC4.
18 REFIO bidirectional DAC voltage reference input/output.
19 CLKGND power_in Clock ground.
20 CLKN input DAC clock input, negative side (differential, with a minimum 150 mV peak-to-peak differential input voltage).
21 CLKP input DAC clock input, positive side (differential, with a minimum 150 mV peak-to-peak differential input voltage).
22 CLDO power_out 1.8 V clock power supply output when the internal clock LDO is in use, or clock power supply input when the internal regulator is bypassed; bypass with a 0.1 µF capacitor when the internal clock LDO is enabled.
23 CLKVDD power_in 1.8 V to 3.3 V clock power supply input.
24 FSADJ2/CAL_SENSE passive External full-scale current output adjust for DAC2 (FSADJ2), and sense input for automatic IOUTFS calibration (CAL_SENSE).
25 FSADJ1 passive External full-scale current output adjust for DAC1, or full-scale current output adjust reference for automatic IOUTFS calibration.
26 AGND power_in Analog ground.
27 IOUTP1 output DAC1 current output, positive side.
28 IOUTN1 output DAC1 current output, negative side.
29 AVDD1 power_in 1.8 V to 3.3 V power supply input for DAC1 and DAC2.
30 IOUTN2 output DAC2 current output, negative side.
31 IOUTP2 output DAC2 current output, positive side.
32 TRIGGER input Pattern trigger input, active low.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer ADI
Package LFCSP-32(5x5)
Category Others
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD1, AVDD2, DVDD to AGND, DGND, CLKGND AVDD1, AVDD2, DVDD -0.3 3.9 V to AGND, DGND, CLKGND 11
CLKVDD to AGND, DGND, CLKGND CLKVDD -0.3 3.9 V to AGND, DGND, CLKGND 11
CLDO, DLDO1, DLDO2 to AGND, DGND, CLKGND CLDO, DLDO1, DLDO2 -0.3 2.2 V to AGND, DGND, CLKGND 11
AGND to DGND, CLKGND AGND -0.3 0.3 V to DGND, CLKGND 11
DGND to AGND, CLKGND DGND -0.3 0.3 V to AGND, CLKGND 11
CLKGND to AGND, DGND CLKGND -0.3 0.3 V to AGND, DGND 11
CS, SDIO, SCLK, SDO/SDI2/DOUT, RESET, TRIGGER to DGND CS, SDIO, SCLK, SDO/SDI2/DOUT, RESET, TRIGGER -0.3 V to DGND; printed upper limit DVDD + 0.3 V 11
CLKP, CLKN to CLKGND CLKP, CLKN -0.3 V to CLKGND; printed upper limit CLKVDD + 0.3 V 11
REFIO to AGND REFIO -1 V to AGND; printed upper limit AVDDx + 0.3 V 11
IOUTP1, IOUTN1, IOUTP2, IOUTN2, IOUTP3, IOUTN3, IOUTP4, IOUTN4 to AGND IOUTP1 to IOUTN4 -0.3 V to AGND; printed upper limit DVDD + 0.3 V 11
FSADJ1, FSADJ2/CAL_SENSE, FS4DJ3, FSADJ4 to AGND FSADJ1, FSADJ2/CAL_SENSE, FS4DJ3, FSADJ4 -0.3 V to AGND; printed upper limit AVDDx + 0.3 V 11
Junction Temperature TJ 125 °C 11
Storage Temperature Range TSTG -65 150 °C 11
Thermal resistance, junction to ambient (CP-32-121) θJA 30.18 °C/W Typical; JEDEC 4-layer 2S2P board, still air 11
Thermal resistance, junction to board (CP-32-121) θJB 6.59 °C/W Typical; JEDEC 4-layer 2S2P board, still air 11
Thermal resistance, junction to case (CP-32-121) θJC 3.84 °C/W Typical; JEDEC 4-layer 2S2P board, still air 11
Supply voltage range, AVDDx, DVDD, CLKVDD (nominal) AVDDx, DVDD, CLKVDD 1.8 3.3 V Stated as 1.8 V to 3.3 V nominal in Theory of Operation text 21

CAD (KiCad official)

  • Symbol: AD9106BCPZ
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: ad9106bcpz-etched.step / ad9106bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9106bcpz.step / ad9106bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ADI datasheet (55 pp, sha256 3801aecf82bc867b, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF