component
AD9059BRSZ
Public Made by Adomby adom
Analog Devices Pre-ordered Chips, SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD9059BRSZ
Analog Devices · Pre-ordered Chips · SSOP-28-208mil
AD9059BRSZ from Analog Devices, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AINA | input | Analog input for ADC A, a 1.0 V p-p input range centered at 2.5 V with 150 kΩ input resistance. |
| 2 | VREF | power_in | Internal 2.5 V voltage reference (typical) that should be bypassed with 0.1 µF to ground, or overdriven by an external reference of up to ±10% gain adjustment. |
| 3 | PWRDN | input | Power-down select; logic HIGH puts the device into power-down mode and drives the digital outputs to high impedance. |
| 4 | VD | power_in | Analog 5 V power supply for the ADCs. |
| 5 | GND | power_in | Ground. |
| 6 | VDD | power_in | Digital output power supply, nominally 3 V to 5 V. |
| 7 | D7A | output | ADC A digital output bit 7 (MSB), offset binary coded. |
| 8 | D6A | output | ADC A digital output bit 6, offset binary coded. |
| 9 | D5A | output | ADC A digital output bit 5, offset binary coded. |
| 10 | D4A | output | ADC A digital output bit 4, offset binary coded. |
| 11 | D3A | output | ADC A digital output bit 3, offset binary coded. |
| 12 | D2A | output | ADC A digital output bit 2, offset binary coded. |
| 13 | D1A | output | ADC A digital output bit 1, offset binary coded. |
| 14 | D0A | output | ADC A digital output bit 0 (LSB), offset binary coded. |
| 15 | D0B | output | ADC B digital output bit 0 (LSB), offset binary coded. |
| 16 | D1B | output | ADC B digital output bit 1, offset binary coded. |
| 17 | D2B | output | ADC B digital output bit 2, offset binary coded. |
| 18 | D3B | output | ADC B digital output bit 3, offset binary coded. |
| 19 | D4B | output | ADC B digital output bit 4, offset binary coded. |
| 20 | D5B | output | ADC B digital output bit 5, offset binary coded. |
| 21 | D6B | output | ADC B digital output bit 6, offset binary coded. |
| 22 | D7B | output | ADC B digital output bit 7 (MSB), offset binary coded. |
| 23 | VDD | power_in | Digital output power supply, nominally 3 V to 5 V. |
| 24 | GND | power_in | Ground. |
| 25 | VD | power_in | Analog 5 V power supply for the ADCs. |
| 26 | ENCODE | input | Encode clock for ADCs A and B; both ADCs sample simultaneously on the rising edge, with up to 60 MSPS conversion rate. |
| 27 | GND | power_in | Ground. |
| 28 | AINB | input | Analog input for ADC B, a 1.0 V p-p input range centered at 2.5 V with 150 kΩ input resistance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SSOP-28-208mil |
| Category | Interface ICs |
| Pins | 28 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gain Error (25°C) | -6 | -2.5 | 6 | % FS | 25°C, test level I | 2 | |
| Gain Error (Full) | -8 | 8 | % FS | Full temperature range, test level VI | 2 | ||
| Differential Nonlinearity (25°C) | 0.75 | 2 | LSB | 25°C, test level I | 2 | ||
| Differential Nonlinearity (Full) | 2.5 | LSB | Full temperature range, test level VI | 2 | |||
| Integral Nonlinearity (25°C) | 0.75 | 2 | LSB | 25°C, test level I | 2 | ||
| Integral Nonlinearity (Full) | 2.5 | LSB | Full temperature range, test level VI | 2 | |||
| Gain Temperature Coefficient | -70 | 70 | ppm/°C | Full temperature range, ADC only with fixed 2.5 V external reference | 2 | ||
| Input Offset Voltage (25°C) | -15 | 0 | 15 | mV | 25°C, test level I | 2 | |
| Input Offset Voltage (Full) | -25 | 25 | mV | Full temperature range, test level VI | 2 | ||
| Input Bias Current | 6 | 16 | µA | 25°C, test level I | 2 | ||
| Band Gap Reference Output Voltage | 2.4 | 2.5 | 2.6 | V | Full temperature range, test level VI | 2 | |
| Band Gap Reference Temperature Coefficient | -10 | 10 | ppm/°C | Full temperature range | 2 | ||
| Channel Gain Delta (A to B) | -1 | 1 | % FS | 25°C | 2 | ||
| Channel Input Offset Voltage Delta (A to B) | -4 | 4 | mV | 25°C | 2 | ||
| Output Valid Time (tV) | tV | 4 | 6.6 | ns | Full temperature range, test level IV, measured from ENCODE 1.5 V level to 10%/90% output levels, ac load 10 pF | 2 | |
| Output Propagation Delay (tPD) | tPD | 9.5 | 14.2 | ns | Full temperature range, test level IV, measured from ENCODE 1.5 V level to 10%/90% output levels, ac load 10 pF | 2 | |
| Encode Pulsewidth High | tEH | 6.7 | 166 | ns | 25°C, test level IV | 3 | |
| Encode Pulsewidth Low | tEL | 6.7 | 166 | ns | 25°C, test level IV | 3 | |
| Logic 1 Voltage (Digital Input) | 2 | V | Full temperature range, test level VI | 3 | |||
| Logic 0 Voltage (Digital Input) | 0.8 | V | Full temperature range, test level VI | 3 | |||
| Logic 1 Input Current | -1 | 1 | µA | Full temperature range, test level VI | 3 | ||
| Logic 0 Input Current | -1 | 1 | µA | Full temperature range, test level VI | 3 | ||
| Logic 1 Output Voltage (VDD = 3 V) | 2.95 | V | VDD = 3 V, full temperature range, test level VI | 3 | |||
| Logic 1 Output Voltage (VDD = 5 V) | 4.95 | V | VDD = 5 V, full temperature range, test level IV | 3 | |||
| Logic 0 Output Voltage | 0.05 | V | VDD = 3 V or 5 V, full temperature range, test level VI | 3 | |||
| VD Supply Current | 72 | 92 | mA | VD = 5 V, full temperature range, test level VI | 3 | ||
| VDD Supply Current | 13 | 15 | mA | VDD = 3 V, full temperature range, test level VI | 3 | ||
| Power Dissipation | 400 | 505 | mW | 60 MSPS encode, 10.3 MHz analog input, full temperature range, test level VI | 3 | ||
| Power-Down Dissipation | 6 | 12 | mW | Full temperature range, test level VI | 3 | ||
| Supply Voltage VD, VDD (absolute maximum) | VD, VDD | 7 | V | Absolute maximum rating | 3 | ||
| Analog Inputs Voltage (absolute maximum) | -0.5 | V | Absolute maximum, upper limit VD + 0.5 V | 3 | |||
| Digital Inputs Voltage (absolute maximum) | -0.5 | V | Absolute maximum, upper limit VD + 0.5 V | 3 | |||
| VREF Input Voltage (absolute maximum) | -0.5 | V | Absolute maximum, upper limit VD + 0.5 V | 3 | |||
| Digital Output Current (absolute maximum) | 20 | mA | Absolute maximum rating | 3 | |||
| Operating Temperature (absolute maximum) | -55 | 125 | °C | Absolute maximum rating | 3 | ||
| Storage Temperature (absolute maximum) | -65 | 150 | °C | Absolute maximum rating | 3 | ||
| Operating Temperature Range (industrial) | -40 | 85 | °C | Ordering guide, AD9059BRS | 3 | ||
| Conversion Rate | 5 | 60 | MSPS | Guaranteed operating conversion rate range | 8 | ||
| Digital Output Supply Voltage (VDD) | VDD | 3 | 5 | V | Nominally 3 V to 5 V | 4 | |
| Thermal Resistance Junction-to-Case | θJC | 39 | °C/W | Typical, RS (SSOP) 28-lead package | 3 | ||
| Thermal Resistance Case-to-Ambient | θCA | 70 | °C/W | Typical, RS (SSOP) 28-lead package | 3 | ||
| Thermal Resistance Junction-to-Ambient | θJA | 109 | °C/W | Typical, RS (SSOP) 28-lead package | 3 |
CAD (KiCad official)
- Symbol:
AD9059BRSZ - Footprint:
Package_SO:SSOP-28_5.3x10.2mm_P0.65mm - 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
- 3D model files:
ad9059brsz-etched.step/ad9059brsz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad9059brsz.step/ad9059brsz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (12 pp, sha256
2d48f26808e90699, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD9059BRSZ
**Analog Devices** · Pre-ordered Chips · SSOP-28-208mil
AD9059BRSZ from Analog Devices, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AINA | input | Analog input for ADC A, a 1.0 V p-p input range centered at 2.5 V with 150 kΩ input resistance. |
| 2 | VREF | power_in | Internal 2.5 V voltage reference (typical) that should be bypassed with 0.1 µF to ground, or overdriven by an external reference of up to ±10% gain adjustment. |
| 3 | PWRDN | input | Power-down select; logic HIGH puts the device into power-down mode and drives the digital outputs to high impedance. |
| 4 | VD | power_in | Analog 5 V power supply for the ADCs. |
| 5 | GND | power_in | Ground. |
| 6 | VDD | power_in | Digital output power supply, nominally 3 V to 5 V. |
| 7 | D7A | output | ADC A digital output bit 7 (MSB), offset binary coded. |
| 8 | D6A | output | ADC A digital output bit 6, offset binary coded. |
| 9 | D5A | output | ADC A digital output bit 5, offset binary coded. |
| 10 | D4A | output | ADC A digital output bit 4, offset binary coded. |
| 11 | D3A | output | ADC A digital output bit 3, offset binary coded. |
| 12 | D2A | output | ADC A digital output bit 2, offset binary coded. |
| 13 | D1A | output | ADC A digital output bit 1, offset binary coded. |
| 14 | D0A | output | ADC A digital output bit 0 (LSB), offset binary coded. |
| 15 | D0B | output | ADC B digital output bit 0 (LSB), offset binary coded. |
| 16 | D1B | output | ADC B digital output bit 1, offset binary coded. |
| 17 | D2B | output | ADC B digital output bit 2, offset binary coded. |
| 18 | D3B | output | ADC B digital output bit 3, offset binary coded. |
| 19 | D4B | output | ADC B digital output bit 4, offset binary coded. |
| 20 | D5B | output | ADC B digital output bit 5, offset binary coded. |
| 21 | D6B | output | ADC B digital output bit 6, offset binary coded. |
| 22 | D7B | output | ADC B digital output bit 7 (MSB), offset binary coded. |
| 23 | VDD | power_in | Digital output power supply, nominally 3 V to 5 V. |
| 24 | GND | power_in | Ground. |
| 25 | VD | power_in | Analog 5 V power supply for the ADCs. |
| 26 | ENCODE | input | Encode clock for ADCs A and B; both ADCs sample simultaneously on the rising edge, with up to 60 MSPS conversion rate. |
| 27 | GND | power_in | Ground. |
| 28 | AINB | input | Analog input for ADC B, a 1.0 V p-p input range centered at 2.5 V with 150 kΩ input resistance. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SSOP-28-208mil |
| Category | Interface ICs |
| Pins | 28 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gain Error (25°C) | | -6 | -2.5 | 6 | % FS | 25°C, test level I | 2 |
| Gain Error (Full) | | -8 | | 8 | % FS | Full temperature range, test level VI | 2 |
| Differential Nonlinearity (25°C) | | | 0.75 | 2 | LSB | 25°C, test level I | 2 |
| Differential Nonlinearity (Full) | | | | 2.5 | LSB | Full temperature range, test level VI | 2 |
| Integral Nonlinearity (25°C) | | | 0.75 | 2 | LSB | 25°C, test level I | 2 |
| Integral Nonlinearity (Full) | | | | 2.5 | LSB | Full temperature range, test level VI | 2 |
| Gain Temperature Coefficient | | -70 | | 70 | ppm/°C | Full temperature range, ADC only with fixed 2.5 V external reference | 2 |
| Input Offset Voltage (25°C) | | -15 | 0 | 15 | mV | 25°C, test level I | 2 |
| Input Offset Voltage (Full) | | -25 | | 25 | mV | Full temperature range, test level VI | 2 |
| Input Bias Current | | | 6 | 16 | µA | 25°C, test level I | 2 |
| Band Gap Reference Output Voltage | | 2.4 | 2.5 | 2.6 | V | Full temperature range, test level VI | 2 |
| Band Gap Reference Temperature Coefficient | | -10 | | 10 | ppm/°C | Full temperature range | 2 |
| Channel Gain Delta (A to B) | | -1 | | 1 | % FS | 25°C | 2 |
| Channel Input Offset Voltage Delta (A to B) | | -4 | | 4 | mV | 25°C | 2 |
| Output Valid Time (tV) | tV | 4 | | 6.6 | ns | Full temperature range, test level IV, measured from ENCODE 1.5 V level to 10%/90% output levels, ac load 10 pF | 2 |
| Output Propagation Delay (tPD) | tPD | 9.5 | | 14.2 | ns | Full temperature range, test level IV, measured from ENCODE 1.5 V level to 10%/90% output levels, ac load 10 pF | 2 |
| Encode Pulsewidth High | tEH | 6.7 | | 166 | ns | 25°C, test level IV | 3 |
| Encode Pulsewidth Low | tEL | 6.7 | | 166 | ns | 25°C, test level IV | 3 |
| Logic 1 Voltage (Digital Input) | | 2 | | | V | Full temperature range, test level VI | 3 |
| Logic 0 Voltage (Digital Input) | | | | 0.8 | V | Full temperature range, test level VI | 3 |
| Logic 1 Input Current | | -1 | | 1 | µA | Full temperature range, test level VI | 3 |
| Logic 0 Input Current | | -1 | | 1 | µA | Full temperature range, test level VI | 3 |
| Logic 1 Output Voltage (VDD = 3 V) | | 2.95 | | | V | VDD = 3 V, full temperature range, test level VI | 3 |
| Logic 1 Output Voltage (VDD = 5 V) | | 4.95 | | | V | VDD = 5 V, full temperature range, test level IV | 3 |
| Logic 0 Output Voltage | | | | 0.05 | V | VDD = 3 V or 5 V, full temperature range, test level VI | 3 |
| VD Supply Current | | | 72 | 92 | mA | VD = 5 V, full temperature range, test level VI | 3 |
| VDD Supply Current | | | 13 | 15 | mA | VDD = 3 V, full temperature range, test level VI | 3 |
| Power Dissipation | | | 400 | 505 | mW | 60 MSPS encode, 10.3 MHz analog input, full temperature range, test level VI | 3 |
| Power-Down Dissipation | | | 6 | 12 | mW | Full temperature range, test level VI | 3 |
| Supply Voltage VD, VDD (absolute maximum) | VD, VDD | | | 7 | V | Absolute maximum rating | 3 |
| Analog Inputs Voltage (absolute maximum) | | -0.5 | | | V | Absolute maximum, upper limit VD + 0.5 V | 3 |
| Digital Inputs Voltage (absolute maximum) | | -0.5 | | | V | Absolute maximum, upper limit VD + 0.5 V | 3 |
| VREF Input Voltage (absolute maximum) | | -0.5 | | | V | Absolute maximum, upper limit VD + 0.5 V | 3 |
| Digital Output Current (absolute maximum) | | | | 20 | mA | Absolute maximum rating | 3 |
| Operating Temperature (absolute maximum) | | -55 | | 125 | °C | Absolute maximum rating | 3 |
| Storage Temperature (absolute maximum) | | -65 | | 150 | °C | Absolute maximum rating | 3 |
| Operating Temperature Range (industrial) | | -40 | | 85 | °C | Ordering guide, AD9059BRS | 3 |
| Conversion Rate | | 5 | | 60 | MSPS | Guaranteed operating conversion rate range | 8 |
| Digital Output Supply Voltage (VDD) | VDD | 3 | | 5 | V | Nominally 3 V to 5 V | 4 |
| Thermal Resistance Junction-to-Case | θJC | | 39 | | °C/W | Typical, RS (SSOP) 28-lead package | 3 |
| Thermal Resistance Case-to-Ambient | θCA | | 70 | | °C/W | Typical, RS (SSOP) 28-lead package | 3 |
| Thermal Resistance Junction-to-Ambient | θJA | | 109 | | °C/W | Typical, RS (SSOP) 28-lead package | 3 |
## CAD (KiCad official)
- Symbol: `AD9059BRSZ`
- Footprint: `Package_SO:SSOP-28_5.3x10.2mm_P0.65mm`
- 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
- 3D model files: `ad9059brsz-etched.step` / `ad9059brsz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad9059brsz.step` / `ad9059brsz.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD9059.pdf) (12 pp, sha256 `2d48f26808e90699`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad9059brsz-datasheet.pdf)