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AD820ANZ

Public Made by Adom

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Analog Devices Pre-ordered Chips, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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AD820ANZ

Analog Devices · Pre-ordered Chips · PDIP-8

AD820ANZ from Analog Devices, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NULL passive Offset-null terminal for the PDIP package, used with a 20 kΩ potentiometer per Figure 46 to trim input offset; the datasheet notes that offset adjustment changes offset drift by 4 μV/°C for every millivolt of induced offset.
2 -IN input Inverting input of the N-channel JFET input stage, where the minimum common-mode range extends 0.2 V below -VS and the input current flows out of the terminal during normal operation.
3 +IN input Noninverting input whose common-mode range extends to 1 V below +VS, and which should have a series resistor (for example 1 kΩ) if the input may exceed +VS by more than 300 mV.
4 -VS power_in Negative supply rail, which is ground in single-supply operation; the part operates from single supplies of 5 V to 30 V or dual supplies of ±2.5 V to ±15 V (features) with an absolute maximum supply of ±18 V.
5 NULL passive Second offset-null terminal of the PDIP package, used together with pin 1 for external offset trimming per Figure 46; the null pins are not functional in the SOIC or MSOP packages.
6 VOUT output Output that swings within 10 mV of the positive rail and 5 mV of the negative rail with no load, sources and sinks a minimum of 15 mA, and drives up to 350 pF of direct capacitive load.
7 +VS power_in Positive supply rail, with single-supply operation from 5 V to 30 V (features) or 5 V to 36 V (general description) and an absolute maximum supply of ±18 V.
8 NC unconnected No connect pin, which is not internally connected on the 8-Lead PDIP package.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package PDIP-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Initial Offset 0.1 0.8 mV VS = 0 V, 5 V; TA = 25°C; VCM = 0 V; VOUT = 0.2 V 3
Maximum Offset over Temperature 0.5 1.2 mV VS = 0 V, 5 V; TMIN to TMAX; VCM = 0 V; VOUT = 0.2 V 3
Input Bias Current 2 25 pA VCM = 0 V to 4 V 3
Input Bias Current at TMAX 0.5 5 nA At TMAX 3
Input Offset Current 2 20 pA 3
Open-Loop Gain, RL = 100 kΩ 400 1000 V/mV VOUT = 0.2 V to 4 V; RL = 100 kΩ 3
Open-Loop Gain, RL = 100 kΩ, TMIN to TMAX 400 V/mV TMIN to TMAX; VOUT = 0.2 V to 4 V; RL = 100 kΩ 3
Open-Loop Gain, RL = 10 kΩ 80 150 V/mV VOUT = 0.2 V to 4 V; RL = 10 kΩ 3
Open-Loop Gain, RL = 10 kΩ, TMIN to TMAX 80 V/mV TMIN to TMAX; VOUT = 0.2 V to 4 V; RL = 10 kΩ 3
Open-Loop Gain, RL = 1 kΩ 15 30 V/mV VOUT = 0.2 V to 4 V; RL = 1 kΩ 3
Open-Loop Gain, RL = 1 kΩ, TMIN to TMAX 10 V/mV TMIN to TMAX; VOUT = 0.2 V to 4 V; RL = 1 kΩ 3
Common-Mode Voltage Range -0.2 4 V TMIN to TMAX 3
CMRR 66 80 dB VCM = 0 V to 2 V 3
CMRR, TMIN to TMAX 66 dB TMIN to TMAX; VCM = 0 V to 2 V 3
Output Saturation Voltage, VOL − VEE VOL − VEE 5 7 mV ISINK = 20 µA 4
Output Saturation Voltage, VOL − VEE, TMIN to TMAX VOL − VEE 10 mV TMIN to TMAX; ISINK = 20 µA 4
Output Saturation Voltage, VCC − VOH VCC − VOH 10 14 mV ISOURCE = 20 µA 4
Output Saturation Voltage, VCC − VOH, TMIN to TMAX VCC − VOH 20 mV TMIN to TMAX; ISOURCE = 20 µA 4
Output Saturation Voltage, VOL − VEE VOL − VEE 40 55 mV ISINK = 2 mA 4
Output Saturation Voltage, VOL − VEE, TMIN to TMAX VOL − VEE 80 mV TMIN to TMAX; ISINK = 2 mA 4
Output Saturation Voltage, VCC − VOH VCC − VOH 80 110 mV ISOURCE = 2 mA 4
Output Saturation Voltage, VCC − VOH, TMIN to TMAX VCC − VOH 160 mV TMIN to TMAX; ISOURCE = 2 mA 4
Output Saturation Voltage, VOL − VEE VOL − VEE 300 500 mV ISINK = 15 mA 4
Output Saturation Voltage, VOL − VEE, TMIN to TMAX VOL − VEE 1000 mV TMIN to TMAX; ISINK = 15 mA 4
Output Saturation Voltage, VCC − VOH VCC − VOH 800 1500 mV ISOURCE = 15 mA 4
Output Saturation Voltage, VCC − VOH, TMIN to TMAX VCC − VOH 1900 mV TMIN to TMAX; ISOURCE = 15 mA 4
Operating Output Current 15 mA 4
Operating Output Current, TMIN to TMAX 12 mA TMIN to TMAX 4
Quiescent Current 620 800 µA TMIN to TMAX; VS = 0 V, 5 V 4
Power Supply Rejection 70 80 dB V+ = 5 V to 15 V 4
Initial Offset 0.1 0.8 mV VS = ±5 V; TA = 25°C; VCM = 0 V; VOUT = 0 V 5
Maximum Offset over Temperature 0.5 1.5 mV VS = ±5 V; TMIN to TMAX; VCM = 0 V; VOUT = 0 V 5
Input Bias Current 2 25 pA VS = ±5 V; VCM = −5 V to +4 V 5
Open-Loop Gain, RL = 10 kΩ 80 150 V/mV VS = ±5 V; VOUT = −4 V to +4 V; RL = 10 kΩ 5
Open-Loop Gain, RL = 1 kΩ 20 30 V/mV VS = ±5 V; VOUT = −4 V to +4 V; RL = 1 kΩ 5
Common-Mode Voltage Range -5.2 4 V VS = ±5 V; TMIN to TMAX 5
CMRR 66 80 dB VS = ±5 V; VCM = −5 V to +2 V 5
Output Saturation Voltage, VOL − VEE VOL − VEE 300 500 mV VS = ±5 V; ISINK = 15 mA 6
Output Saturation Voltage, VCC − VOH VCC − VOH 800 1500 mV VS = ±5 V; ISOURCE = 15 mA 6
Quiescent Current 650 800 µA VS = ±5 V; TMIN to TMAX 6
Power Supply Rejection 70 80 dB VS = ±5 V; V+ = 5 V to 15 V 6
Initial Offset 0.4 2 mV VS = ±15 V; TA = 25°C; VCM = 0 V; VOUT = 0 V 7
Maximum Offset over Temperature 0.5 3 mV VS = ±15 V; TMIN to TMAX; VCM = 0 V; VOUT = 0 V 7
Input Bias Current 2 25 pA VS = ±15 V; VCM = 0 V 7
Open-Loop Gain, RL = 10 kΩ 100 500 V/mV VS = ±15 V; VOUT = −10 V to +10 V; RL = 10 kΩ 7
Open-Loop Gain, RL = 1 kΩ 30 45 V/mV VS = ±15 V; VOUT = −10 V to +10 V; RL = 1 kΩ 7
Common-Mode Voltage Range -15.2 14 V VS = ±15 V; TMIN to TMAX 7
CMRR 70 80 dB VS = ±15 V; VCM = −15 V to +12 V 7
Operating Output Current 20 mA VS = ±15 V 8
Quiescent Current 700 900 µA VS = ±15 V; TMIN to TMAX 8
Power Supply Rejection 70 80 dB VS = ±15 V; V+ = 5 V to 15 V 8
Supply Voltage -18 18 V Absolute maximum, printed as ±18 V 9
Differential Input Voltage -30 30 V 9
Internal Power Dissipation 1.6 W 8-Lead PDIP (N) 9
Storage Temperature Range -65 125 °C 8-Lead PDIP (N) 9
Operating Temperature Range -40 85 °C AD820A/AD820B 9
Lead Temperature (Soldering) 260 °C Soldering, 60 sec 9
Thermal Resistance, Junction-to-Ambient θJA 90 °C/W 8-Lead PDIP (N) 9

CAD (KiCad official)

  • Symbol: AD820ANZ
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: PDIP-8 (KiCad packages3D, STEP)
  • 3D model files: ad820anz-etched.step / ad820anz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad820anz.step / ad820anz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 fb2c28aa128b3e0d, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF