component
AD7924BRUZ-REEL7
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"description": "Analog Devices Analog To Digital Converters (ADC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"data acquisition",
"ad7924bruz-reel7",
"factory-2.0.0",
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"component": {
"mpn": "AD7924BRUZ-REEL7",
"manufacturer": "Analog Devices",
"package": "TSSOP-16",
"pin_count": 16,
"category": "Data Acquisition",
"subcategory": "Analog To Digital Converters (ADC)",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885735479263232",
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"lbr": "ad7924bruz-reel7.lbr"
},
"distributor_links": {
"lcsc": "C652040",
"digikey": "AD7924BRUZ-REEL7TR-ND",
"mouser": "584-AD7924BRUZ-R7"
},
"distributor_check": {
"checked_at": "2026-10-18T06:44:50Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "AD7924BRUZ-REEL7TR-ND",
"status": "found"
},
"mouser": {
"pn": "584-AD7924BRUZ-R7",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "SCLK",
"type": "input",
"description": "Serial clock logic input that accesses the device data and also acts as the clock source for the conversion process."
},
{
"number": "2",
"name": "DIN",
"type": "input",
"description": "Serial data logic input that loads the control register on SCLK falling edges, with the first 12 clocks after CS falls loading the register when the WRITE bit is 1."
},
{
"number": "3",
"name": "CS",
"type": "input",
"description": "Active-low logic chip select that starts a conversion on its falling edge and enables serial data frame transfer."
},
{
"number": "4",
"name": "AGND",
"type": "power_in",
"description": "Analog ground reference for all analog circuitry; all AGND pins should be connected together and returned to the AGND plane."
},
{
"number": "5",
"name": "AVDD",
"type": "power_in",
"description": "Analog supply input with a range of 2.7 V to 5.25 V, where the 0 V to 2 × REFIN input range requires 4.75 V to 5.25 V."
},
{
"number": "6",
"name": "AVDD",
"type": "power_in",
"description": "Analog supply input with a range of 2.7 V to 5.25 V, where the 0 V to 2 × REFIN input range requires 4.75 V to 5.25 V."
},
{
"number": "7",
"name": "REFIN",
"type": "input",
"description": "External reference voltage input that must be driven with 2.5 V ±1% for rated performance and should be decoupled with at least 0.1 µF."
},
{
"number": "8",
"name": "AGND",
"type": "power_in",
"description": "Analog ground reference for all analog circuitry; all AGND pins should be connected together and returned to the AGND plane."
},
{
"number": "9",
"name": "VIN3",
"type": "input",
"description": "Single-ended analog input channel 3, multiplexed to the sample-and-hold with a 0 V to REFIN or 0 V to 2 × REFIN range; unused channels should be tied to AGND."
},
{
"number": "10",
"name": "VIN2",
"type": "input",
"description": "Single-ended analog input channel 2, multiplexed to the sample-and-hold with a 0 V to REFIN or 0 V to 2 × REFIN range; unused channels should be tied to AGND."
},
{
"number": "11",
"name": "VIN1",
"type": "input",
"description": "Single-ended analog input channel 1, multiplexed to the sample-and-hold with a 0 V to REFIN or 0 V to 2 × REFIN range; unused channels should be tied to AGND."
},
{
"number": "12",
"name": "VIN0",
"type": "input",
"description": "Single-ended analog input channel 0, multiplexed to the sample-and-hold with a 0 V to REFIN or 0 V to 2 × REFIN range; unused channels should be tied to AGND."
},
{
"number": "13",
"name": "AGND",
"type": "power_in",
"description": "Analog ground reference for all analog circuitry; all AGND pins should be connected together and returned to the AGND plane."
},
{
"number": "14",
"name": "DOUT",
"type": "tri_state",
"description": "Serial data output that delivers the conversion result MSB first on SCLK falling edges and returns to three-state when the transfer is complete."
},
{
"number": "15",
"name": "VDRIVE",
"type": "power_in",
"description": "Logic interface supply input that sets the serial interface voltage and must not exceed AVDD by more than 0.3 V."
},
{
"number": "16",
"name": "AGND",
"type": "power_in",
"description": "Analog ground reference for all analog circuitry; all AGND pins should be connected together and returned to the AGND plane."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The pin-to-number mapping was taken from Table 6 (pin function description table) on page 11, becaus; The datasheet is the Chinese translation (Rev. C); pin descriptions were written from the translated; Pins 5 and 6 (AVDD) and pins 4, 8, 13, 16 (AGND) are shared-function pins listed as grouped in Table"
],
"pages_sent": 21,
"cost_usd": 0.1294,
"at": "2026-10-18T06:42:32"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885735479263232",
"pages": 32,
"sha256": "6cf537b28273a2f4",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
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