component

AD7924BRUZ-REEL7

Public Made by Adom

by adom

Analog Devices Analog To Digital Converters (ADC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitionad7924bruz-reel7factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
ad7924bruz-reel7 / README.md
History Download
Ray Publish 0.1.0 c4a31a2 8d ago

AD7924BRUZ-REEL7

Analog Devices · Analog To Digital Converters (ADC) · TSSOP-16

AD7924BRUZ-REEL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCLK input Serial clock logic input that accesses the device data and also acts as the clock source for the conversion process.
2 DIN input Serial data logic input that loads the control register on SCLK falling edges, with the first 12 clocks after CS falls loading the register when the WRITE bit is 1.
3 CS input Active-low logic chip select that starts a conversion on its falling edge and enables serial data frame transfer.
4 AGND power_in Analog ground reference for all analog circuitry; all AGND pins should be connected together and returned to the AGND plane.
5 AVDD power_in Analog supply input with a range of 2.7 V to 5.25 V, where the 0 V to 2 × REFIN input range requires 4.75 V to 5.25 V.
6 AVDD power_in Analog supply input with a range of 2.7 V to 5.25 V, where the 0 V to 2 × REFIN input range requires 4.75 V to 5.25 V.
7 REFIN input External reference voltage input that must be driven with 2.5 V ±1% for rated performance and should be decoupled with at least 0.1 µF.
8 AGND power_in Analog ground reference for all analog circuitry; all AGND pins should be connected together and returned to the AGND plane.
9 VIN3 input Single-ended analog input channel 3, multiplexed to the sample-and-hold with a 0 V to REFIN or 0 V to 2 × REFIN range; unused channels should be tied to AGND.
10 VIN2 input Single-ended analog input channel 2, multiplexed to the sample-and-hold with a 0 V to REFIN or 0 V to 2 × REFIN range; unused channels should be tied to AGND.
11 VIN1 input Single-ended analog input channel 1, multiplexed to the sample-and-hold with a 0 V to REFIN or 0 V to 2 × REFIN range; unused channels should be tied to AGND.
12 VIN0 input Single-ended analog input channel 0, multiplexed to the sample-and-hold with a 0 V to REFIN or 0 V to 2 × REFIN range; unused channels should be tied to AGND.
13 AGND power_in Analog ground reference for all analog circuitry; all AGND pins should be connected together and returned to the AGND plane.
14 DOUT tri_state Serial data output that delivers the conversion result MSB first on SCLK falling edges and returns to three-state when the transfer is complete.
15 VDRIVE power_in Logic interface supply input that sets the serial interface voltage and must not exceed AVDD by more than 0.3 V.
16 AGND power_in Analog ground reference for all analog circuitry; all AGND pins should be connected together and returned to the AGND plane.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16
Category Data Acquisition
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Signal-to-noise and distortion (SINAD), B grade, 5 V SINAD 70 dB 5 V, B型 7
SINAD, B grade, 3 V SINAD 69 dB 3 V 7
Signal-to-noise ratio (SNR), B grade SNR 70 dB B型 7
Total harmonic distortion (THD), 5 V THD -77 dB 5 V 7
Total harmonic distortion (THD), 3 V THD -73 dB 3 V 7
Peak harmonic or spurious noise (SFDR), 5 V SFDR -78 dB 5 V 7
Integral nonlinearity (INL) INL -1 1 LSB 7
Differential nonlinearity (DNL) DNL -0.9 1.5 LSB 保证12位无失码 7
Offset error -8 8 LSB 7
Offset error matching -0.5 0.5 LSB 7
Gain error -1.5 1.5 LSB 7
Gain error matching -0.5 0.5 LSB 7
Positive gain error -1.5 1.5 LSB 7
Positive gain error matching -0.5 0.5 LSB 7
Zero code error -8 8 LSB 7
Zero code error matching -0.5 0.5 LSB 7
Negative gain error -1 1 LSB 7
Negative gain error matching -0.5 0.5 LSB 7
Analog input DC leakage current -1 1 μA 7
REFIN input voltage tolerance (2.5 V nominal) -1 1 % 2.5 V, 额定性能 7
REFIN DC leakage current -1 1 μA 7
Input high voltage (0.7 × VDRIVE) VINH 0.7 V 7
Input low voltage (0.3 × VDRIVE) VINL 0.3 V 7
Digital input current IIN -1 1 μA VIN = 0 V或VDRIVE 7
Output low voltage VOL 0.4 V ISINK = 200 μA 8
Floating-state leakage current -1 1 μA 8
Conversion time 800 ns 16个SCLK周期(SCLK为20 MHz) 8
Acquisition time, sine wave input 300 ns 正弦波输入 8
Acquisition time, full-scale step input 300 ns 满量程阶跃输入 8
Throughput rate 1 MSPS 参见串行接口部分 8
VDD supply range VDD 2.7 5.25 V 8
VDRIVE supply range VDRIVE 2.7 5.25 V 8
Normal mode operating supply current IDD 2.7 mA AVDD = 4.75 V至5.25 V, fSCLK = 20 MHz 8
Normal mode operating supply current (AD7924 as printed) IDD 2 mA AVDD = 4.75 V至5.25 V, fSCLK = 20 MHz 8
Auto power-down mode supply current, static IDD 0.5 μA 静态 8
Full power-down mode supply current IDD 0.5 μA SCLK开启或关闭 8
Power consumption, normal mode operating 13.5 mW AVDD = 5 V, fSCLK = 20 MHz 8
Power consumption, normal mode operating 6 mW AVDD = 3 V, fSCLK = 20 MHz 8
Power consumption, auto power-down mode (static) 2.5 μW AVDD = 5 V 8
Power consumption, auto power-down mode (static) 1.5 μW AVDD = 3 V 8
Power consumption, full power-down mode 2.5 μW AVDD = 5 V 8
Power consumption, full power-down mode 1.5 μW AVDD = 3 V 8
SCLK frequency, minimum fSCLK 10 kHz 9
SCLK frequency, maximum fSCLK 20 MHz 9
Quiet time between CS rising and next conversion start tQUIET 50 ns 9
CS to SCLK setup time t2 10 ns 9
CS to DOUT three-state disable delay t3 35 ns AVDD = 3 V 9
CS to DOUT three-state disable delay t3 30 ns AVDD = 5 V 9
Data access time after SCLK falling edge t4 40 ns 9
SCLK low pulse width t5 0.4 × tSCLK 9
SCLK high pulse width t6 0.4 × tSCLK 9
SCLK to DOUT valid hold time t7 10 ns 9
SCLK falling edge to DOUT high impedance (bus relinquish time) t8 15 45 ns AVDD = 3 V 9
SCLK falling edge to DOUT high impedance (bus relinquish time) t8 15 35 ns AVDD = 5 V 9
DIN setup time before SCLK falling edge t9 10 ns 9
DIN hold time after SCLK falling edge t10 5 ns 9
16th SCLK falling edge to CS high t11 20 ns 9
Power-up time from full or auto power-down mode t12 1 μs 完全关断/自动关断模式上电时间 9
Thermal resistance, junction to ambient (TSSOP) θJA 150.4 °C/W TSSOP 10
Thermal resistance, junction to case (TSSOP) θJC 27.6 °C/W TSSOP 10

CAD (KiCad official)

  • Symbol: AD7924BRUZ-REEL7
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ad7924bruz-reel7-etched.step / ad7924bruz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7924bruz-reel7.step / ad7924bruz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (32 pp, sha256 6cf537b28273a2f4, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF