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AD7923BRUZ-REEL7
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Analog Devices Analog To Digital Converters (ADC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README
markdownAD7923BRUZ-REEL7
Analog Devices · Analog To Digital Converters (ADC) · TSSOP-16
AD7923BRUZ-REEL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock logic input that provides the serial clock for accessing data and is also the master clock for the conversion process. |
| 2 | DIN | input | Data in logic input; data written to the control register is clocked in on the falling edge of SCLK. |
| 3 | CS | input | Active-low logic chip select that initiates conversions and frames the serial data transfer, with the input sampled on its falling edge. |
| 4 | AGND | power_in | Analog ground reference for all analog circuitry; all AGND pins should be connected together and analog inputs and external reference are referred to this pin. |
| 5 | AVDD | power_in | Analog power supply input with a range of 2.7 V to 5.25 V, which must be 4.75 V to 5.25 V for the 0 V to 2 × REFIN input range. |
| 6 | AVDD | power_in | Analog power supply input with a range of 2.7 V to 5.25 V, which must be 4.75 V to 5.25 V for the 0 V to 2 × REFIN input range. |
| 7 | REFIN | input | External reference input that must be applied at 2.5 V ±1% for specified performance. |
| 8 | AGND | power_in | Analog ground reference for all analog circuitry; all AGND pins should be connected together and analog inputs and external reference are referred to this pin. |
| 9 | VIN3 | input | Single-ended analog input channel 3 multiplexed into the track-and-hold, with range 0 V to REFIN or 0 V to 2 × REFIN; unused inputs must be connected to AGND. |
| 10 | VIN2 | input | Single-ended analog input channel 2 multiplexed into the track-and-hold, with range 0 V to REFIN or 0 V to 2 × REFIN; unused inputs must be connected to AGND. |
| 11 | VIN1 | input | Single-ended analog input channel 1 multiplexed into the track-and-hold, with range 0 V to REFIN or 0 V to 2 × REFIN; unused inputs must be connected to AGND. |
| 12 | VIN0 | input | Single-ended analog input channel 0 multiplexed into the track-and-hold, with range 0 V to REFIN or 0 V to 2 × REFIN; unused inputs must be connected to AGND. |
| 13 | AGND | power_in | Analog ground reference for all analog circuitry; all AGND pins should be connected together and analog inputs and external reference are referred to this pin. |
| 14 | DOUT | output | Logic data output that delivers the conversion result as a serial stream (two leading 0s, two channel address bits, then 12 data bits MSB first), clocked out on the SCLK falling edge. |
| 15 | VDRIVE | power_in | Logic power supply input that sets the voltage at which the serial interface operates, independent of AVDD. |
| 16 | AGND | power_in | Analog ground reference for all analog circuitry; all AGND pins should be connected together and analog inputs and external reference are referred to this pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| SINAD (B version, 5 V, -40 to +85 C) | SINAD | 70 | dB | @ 5 V, -40°C to +85°C | 3 | ||
| SINAD (B version, 5 V, 85 to 125 C) | SINAD | 69 | 70 | dB | @ 5 V, 85°C to 125°C | 3 | |
| SINAD (B version, 3 V) | SINAD | 69 | 70 | dB | @ 3 V, -40°C to +125°C | 3 | |
| Signal-to-Noise (SNR) | SNR | 70 | dB | 3 | |||
| Total Harmonic Distortion (5 V) | THD | -84 | -77 | dB | @ 5 V | 3 | |
| Total Harmonic Distortion (3 V) | THD | -77 | -73 | dB | @ 3 V | 3 | |
| Peak Harmonic or Spurious Noise (5 V) | SFDR | -86 | -78 | dB | @ 5 V | 3 | |
| Peak Harmonic or Spurious Noise (3 V) | SFDR | -80 | -76 | dB | @ 3 V | 3 | |
| Integral Nonlinearity | INL | -1 | 1 | LSB | 3 | ||
| Differential Nonlinearity | DNL | -0.9 | 1.5 | LSB | Guaranteed no missed codes to 12 bits | 3 | |
| Offset Error | -8 | 0.5 | 8 | LSB | 0 V to REFIN input range; straight binary output coding | 3 | |
| Gain Error | -1.5 | 1.5 | LSB | 0 V to REFIN input range; straight binary output coding | 3 | ||
| Positive Gain Error | -1.5 | 1.5 | LSB | 0 V to 2 × REFIN input range; twos complement output coding | 3 | ||
| Zero-Code Error | -8 | 0.8 | 8 | LSB | 0 V to 2 × REFIN input range; twos complement output coding | 3 | |
| Negative Gain Error | -1 | 1 | LSB | 0 V to 2 × REFIN input range; twos complement output coding | 3 | ||
| DC Leakage Current (analog input) | -1 | 1 | µA | 3 | |||
| REFIN Input Voltage tolerance | REFIN | -1 | 1 | % | REFIN = 2.5 V, specified performance | 3 | |
| DC Leakage Current (REFIN) | -1 | 1 | µA | 3 | |||
| Input High Voltage | VINH | 0.7 | × VDRIVE V | 3 | |||
| Input Low Voltage | VINL | 0.3 | × VDRIVE V | 3 | |||
| Input Current | IIN | -1 | 1 | µA | VIN = 0 V or VDRIVE | 3 | |
| Output High Voltage (relative to VDRIVE) | VOH | -0.2 | V (VDRIVE, 0.2 V) | ISOURCE = 200 µA, AVDD = 2.7 V to 5.25 V | 4 | ||
| Output Low Voltage | VOL | 0.4 | V | ISINK = 200 µA | 4 | ||
| Floating-State Leakage Current | -1 | 1 | µA | 4 | |||
| Track-and-Hold Acquisition Time (16 SCLK cycles) | 800 | ns | 16 SCLK cycles with SCLK at 20 MHz | 4 | |||
| Track-and-Hold Acquisition Time (sinewave input) | 300 | ns | Sinewave input | 4 | |||
| Track-and-Hold Acquisition Time (full-scale step) | 300 | ns | Full-scale step input | 4 | |||
| Throughput Rate | 200 | kSPS | 4 | ||||
| AVDD supply range | AVDD | 2.7 | 5.25 | V | 4 | ||
| VDRIVE supply range | VDRIVE | 2.7 | 5.25 | V | 4 | ||
| IDD during conversion (5 V) | IDD | 2.7 | mA | AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz | 4 | ||
| IDD during conversion (3 V) | IDD | 2 | mA | AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz | 4 | ||
| Normal Mode (Operational) current (5 V) | IDD | 1.5 | mA | fSAMPLE = 200 kSPS, AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz | 4 | ||
| Normal Mode (Operational) current (3 V) | IDD | 1.2 | mA | fSAMPLE = 200 kSPS, AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz | 4 | ||
| Auto Shutdown (Static) current | IDD | 0.5 | µA | SCLK on or off | 4 | ||
| Full Shutdown Mode current | IDD | 0.5 | µA | SCLK on or off | 4 | ||
| AVDD to AGND | AVDD | -0.3 | 7 | V | Referenced to AGND | 6 | |
| VDRIVE to AGND | VDRIVE | -0.3 | V | Upper limit AVDD + 0.3 V as printed | 6 | ||
| Analog Input Voltage to AGND | VIN | -0.3 | V | Upper limit AVDD + 0.3 V as printed | 6 | ||
| Digital Input Voltage to AGND | -0.3 | 7 | V | 6 | |||
| Digital Output Voltage to AGND | -0.3 | V | Upper limit AVDD + 0.3 V as printed | 6 | |||
| REFIN to AGND | REFIN | -0.3 | V | Upper limit AVDD + 0.3 V as printed | 6 | ||
| Input Current to Any Pin Except Supplies | -10 | 10 | mA | Transient currents up to 100 mA do not cause SCR latchup | 6 | ||
| Operating Temperature Range (Commercial, B Version) | -40 | 125 | °C | B Version | 6 | ||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Junction Temperature | 150 | °C | 6 | ||||
| TSSOP Package Power Dissipation | 450 | mW | TSSOP package | 6 | |||
| θJA Thermal Impedance (TSSOP) | θJA | 150.4 | °C/W | TSSOP package; value printed without min/typ/max qualifier | 6 | ||
| θJC Thermal Impedance (TSSOP) | θJC | 27.6 | °C/W | TSSOP package; value printed without min/typ/max qualifier | 6 | ||
| ESD (human body model rating) | 1.5 | kV | 6 | ||||
| SCLK frequency | fSCLK | 10 | kHz | AVDD = 3 V and 5 V | 5 | ||
| SCLK frequency | fSCLK | 20 | MHz | AVDD = 3 V and 5 V | 5 | ||
| Minimum quiet time between CS rising edge and next conversion | tQUIET | 50 | ns | AVDD = 3 V and 5 V | 5 | ||
| Delay from CS until DOUT three-state disabled | t3 | 35 | ns | AVDD = 3 V | 5 | ||
| Delay from CS until DOUT three-state disabled | t3 | 30 | ns | AVDD = 5 V | 5 | ||
| Data access time after SCLK falling edge | t4 | 40 | ns | AVDD = 3 V | 5 | ||
| SCLK falling edge to DOUT high impedance | t8 | 15 | 45 | ns | AVDD = 3 V | 5 | |
| SCLK falling edge to DOUT high impedance | t8 | 15 | 35 | ns | AVDD = 5 V | 5 | |
| Power-Up time from full power-down/auto shutdown mode | t12 | 1 | µs | 5 |
CAD (KiCad official)
- Symbol:
AD7923BRUZ-REEL7 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ad7923bruz-reel7-etched.step/ad7923bruz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7923bruz-reel7.step/ad7923bruz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
8061a862635d9c55, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).