AD7918BRUZ from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SCLK	input	Serial clock logic input that clocks data out of the part and serves as the clock source for the conversion process.
2	DIN	input	Data in logic input; control register data is clocked in on the falling edge of SCLK.
3	CS	input	Active-low chip select that initiates conversions and frames the serial data transfer.
4	AGND	power_in	Analog ground reference for all analog circuitry, analog inputs and external reference; all AGND pins must be connected together.
5	AVDD	power_in	Analog power supply input, 2.7 V to 5.25 V (4.75 V to 5.25 V for the 0 V to 2 × REFIN range).
6	AVDD	power_in	Analog power supply input, 2.7 V to 5.25 V (4.75 V to 5.25 V for the 0 V to 2 × REFIN range).
7	REFIN	input	External reference input that must be applied, 2.5 V ± 1% for specified performance.
8	AGND	power_in	Analog ground reference for all analog circuitry, analog inputs and external reference; all AGND pins must be connected together.
9	VIN7	input	Single-ended analog input channel 7, range 0 V to REFIN or 0 V to 2 × REFIN per RANGE bit; connect to AGND if unused.
10	VIN6	input	Single-ended analog input channel 6, range 0 V to REFIN or 0 V to 2 × REFIN per RANGE bit; connect to AGND if unused.
11	VIN5	input	Single-ended analog input channel 5, range 0 V to REFIN or 0 V to 2 × REFIN per RANGE bit; connect to AGND if unused.
12	VIN4	input	Single-ended analog input channel 4, range 0 V to REFIN or 0 V to 2 × REFIN per RANGE bit; connect to AGND if unused.
13	VIN3	input	Single-ended analog input channel 3, range 0 V to REFIN or 0 V to 2 × REFIN per RANGE bit; connect to AGND if unused.
14	VIN2	input	Single-ended analog input channel 2, range 0 V to REFIN or 0 V to 2 × REFIN per RANGE bit; connect to AGND if unused.
15	VIN1	input	Single-ended analog input channel 1, range 0 V to REFIN or 0 V to 2 × REFIN per RANGE bit; connect to AGND if unused.
16	VIN0	input	Single-ended analog input channel 0, range 0 V to REFIN or 0 V to 2 × REFIN per RANGE bit; connect to AGND if unused.
17	AGND	power_in	Analog ground reference for all analog circuitry, analog inputs and external reference; all AGND pins must be connected together.
18	DOUT	output	Serial data output, MSB first, clocked out on the falling edge of SCLK; for the AD7918 it is one leading zero, three channel address bits, 10 conversion bits and two trailing zeros.
19	VDRIVE	power_in	Logic power supply input that sets the voltage at which the serial interface operates.
20	AGND	power_in	Analog ground reference for all analog circuitry, analog inputs and external reference; all AGND pins must be connected together.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-20
Category	Data Converters
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Output Low Voltage	VOL			0.4	V	ISINK = 200 μA	8
Floating-State Leakage Current		-1		1	μA		8
Floating-State Output Capacitance				10	pF	Sample tested @ 25°C	8
Conversion Time				800	ns	16 SCLK cycles with SCLK at 20 MHz	8
Track-and-Hold Acquisition Time (sine wave input)				300	ns	Sine wave input	8
Track-and-Hold Acquisition Time (step input)				300	ns	Full-scale step input	8
Throughput Rate				1	MSPS	See Serial Interface section	8
Supply Voltage AVDD	AVDD	2.7		5.25	V		8
Logic Supply Voltage VDRIVE	VDRIVE	2.7		5.25	V		8
IDD Normal Mode (Operational), 5 V	IDD			2.7	mA	AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz	8
IDD Normal Mode (Operational), 3 V	IDD			2	mA	AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz	8
IDD Auto Shutdown Mode (Static)	IDD			0.5	μA	Static	8
IDD Full Shutdown Mode	IDD			0.5	μA	SCLK on or off (20 nA typ)	8
Power Dissipation Normal Mode, 5 V				13.5	mW	AVDD = 5 V, fSCLK = 20 MHz	8
Power Dissipation Normal Mode, 3 V				6	mW	AVDD = 3 V, fSCLK = 20 MHz	8
Power Dissipation Auto Shutdown (Static), 5 V				2.5	μW	AVDD = 5 V	8
Power Dissipation Auto Shutdown (Static), 3 V				1.5	μW	AVDD = 3 V	8
Power Dissipation Full Shutdown, 5 V				2.5	μW	AVDD = 5 V	8
Power Dissipation Full Shutdown, 3 V				1.5	μW	AVDD = 3 V	8
SCLK Frequency (min)	fSCLK	10			kHz	AVDD = 3 V and 5 V	9
SCLK Frequency (max)	fSCLK			20	MHz	AVDD = 3 V and 5 V	9
Quiet time between CS rising edge and next conversion	tQUIET	50			ns	AVDD = 3 V and 5 V	9
CS to SCLK setup time	t2	10			ns	AVDD = 3 V and 5 V	9
Delay from CS until DOUT three-state disabled, 3 V	t3			35	ns	AVDD = 3 V	9
Delay from CS until DOUT three-state disabled, 5 V	t3			30	ns	AVDD = 5 V	9
Data access time after SCLK falling edge	t4			40	ns	AVDD = 3 V and 5 V	9
SCLK to DOUT valid hold time	t7	10			ns	AVDD = 3 V and 5 V	9
SCLK falling edge to DOUT high impedance, 3 V	t8	15		45	ns	AVDD = 3 V	9
SCLK falling edge to DOUT high impedance, 5 V	t8	15		35	ns	AVDD = 5 V	9
DIN setup time prior to SCLK falling edge	t9	10			ns	AVDD = 3 V and 5 V	9
DIN hold time after SCLK falling edge	t10	5			ns	AVDD = 3 V and 5 V	9
16th SCLK falling edge to CS high	t11	20			ns	AVDD = 3 V and 5 V	9
Power-up time from full power-down/auto shutdown	t12			1	μs	AVDD = 3 V and 5 V	9
AVDD to AGND	AVDD	-0.3		7	V	TA = 25°C	10
VDRIVE to AGND	VDRIVE	-0.3			V	Max is AVDD + 0.3 V; TA = 25°C	10
Analog Input Voltage to AGND		-0.3			V	Max is AVDD + 0.3 V; TA = 25°C	10
Digital Input Voltage to AGND		-0.3		7	V	TA = 25°C	10
Digital Output Voltage to AGND		-0.3			V	Max is AVDD + 0.3 V; TA = 25°C	10
REFIN to AGND	REFIN	-0.3			V	Max is AVDD + 0.3 V; TA = 25°C	10
Input Current to Any Pin Except Supplies		-10		10	mA	Transient currents of up to 100 mA do not cause SCR latch-up	10
Operating Temperature Range (Commercial, B Version)		-40		85	°C		10
Storage Temperature Range		-65		150	°C		10
Junction Temperature				150	°C		10
TSSOP Package Power Dissipation				450	mW		10
Lead Temperature, Soldering, Vapor Phase				215	°C	60 sec	10
Lead Temperature, Soldering, Infrared				220	°C	15 sec	10
ESD				1.5	kV		10
Thermal Impedance Junction-to-Ambient	θJA		143		°C/W	TSSOP	10
Thermal Impedance Junction-to-Case	θJC		45		°C/W	TSSOP	10
IDD Normal Mode (Static)	IDD		600		μA	AVDD = 2.7 V to 5.25 V, SCLK on or off	8
IDD Using Auto Shutdown Mode	IDD		960		μA	fSAMPLE = 250 kSPS	8

CAD (KiCad official)

Symbol: AD7918BRUZ
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: ad7918bruz-etched.step / ad7918bruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7918bruz.step / ad7918bruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 8d3a9b226094694a, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD7918BRUZ

Verified AD7918BRUZ

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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