AD7896ARZ from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VIN	power_in	Analog input with an input range of 0 V to VDD.
2	VDD	power_in	Positive supply voltage, 2.7 V to 5.5 V, also used as the reference for the part.
3	AGND	power_in	Analog ground, the ground reference for the track-and-hold, comparator, and DAC.
4	SCLK	input	Serial clock input that clocks out a new serial data bit on each falling edge, with data valid for 10 ns after the falling edge; it should be taken low at the end of the serial data transmission.
5	SDATA	tri_state	Serial data output providing sixteen bits (four leading zeros then 12 bits of straight binary conversion data) clocked out on SCLK falling edges, and three-stated after the 16th falling edge.
6	DGND	power_in	Digital ground, the ground reference for digital circuitry.
7	CONVST	input	Edge-triggered convert start input; the falling edge puts the track-and-hold in hold mode and starts conversion, if low at end of conversion the part powers down, and the rising edge wakes it up.
8	BUSY	output	Busy indicator that goes high on the falling edge of CONVST and returns low when the conversion is complete.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOIC-8
Category	ADC/DAC/Data Conversion
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Signal-to-(Noise + Distortion) Ratio @ 25°C	SNR	70			dB	fIN = 10 kHz sine wave, fSAMPLE = 100 kHz	2
Signal-to-(Noise + Distortion) Ratio TMIN to TMAX	SNR	70			dB	TMIN to TMAX	2
Peak Harmonic or Spurious Noise				-80	dB	fIN = 10 kHz sine wave, fSAMPLE = 100 kHz	2
Intermodulation Distortion Third Order Terms	IMD			-80	dB	fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 100 kHz	2
Resolution		12		12	Bits		2
Minimum Resolution for No Missing Codes		12			Bits		2
Relative Accuracy		-1		1	LSB		2
Differential Nonlinearity		-1		1	LSB		2
Positive Full-Scale Error		-3		3	LSB		2
Unipolar Offset Error		-4		4	LSB	VDD = 5 V ± 10%	2
Analog Input Current		-2		2	µA		2
Input High Voltage	VINH	2			V	VDD = 2.7 V to 3.6 V	2
Input High Voltage	VINH	2.4			V	VDD = 5 V ± 10%	2
Input Low Voltage	VINL			0.8	V		2
Logic Input Current	IIN	-10		10	µA	VIN = 0 V to VDD	2
Input Capacitance	CIN			10	pF	Sample tested @ 25°C	2
Output High Voltage	VOH	2.4			V	ISOURCE = 400 µA	2
Output Low Voltage	VOL			0.4	V	ISINK = 1.6 mA	2
Conversion Time Mode 1				8	µs	Mode 1 Operation	2
Conversion Time Mode 2				14	µs	Mode 2 Operation	2
Track-and-Hold Acquisition Time				1.5	µs		2
Supply Voltage	VDD	2.7		5.5	V		3
Supply Current	IDD			4	mA	Digital Input @ DGND, VDD = 2.7 V to 3.6 V	3
Supply Current	IDD			5	mA	Digital Inputs @ DGND, VDD = 5 V ± 10%	3
Power Dissipation			9	10.8	mW	VDD = 2.7 V, Typically 9 mW	3
Power-Down IDD @ 25°C	IDD			5	µA	VDD = 2.7 V to 3.6 V, Digital Inputs @ DGND	3
Power-Down IDD TMIN to TMAX	IDD			15	µA	VDD = 2.7 V to 3.6 V, Digital Inputs @ DGND	3
Power-Down IDD @ 25°C	IDD			50	µA	VDD = 5 V ± 10%, Digital Inputs @ DGND	3
Power-Down IDD TMIN to TMAX	IDD			150	µA	VDD = 5 V ± 10%, Digital Inputs @ DGND	3
Power-Down Power Dissipation @ 25°C				13.5	µW	VDD = 2.7 V	3
CONVST Pulsewidth	t1	40			ns		3
SCLK High Pulsewidth	t2	40			ns		3
SCLK Low Pulsewidth	t3	40			ns		3
Data Access Time after Falling Edge of SCLK	t4			60	ns	VDD = 5 V ± 10%	3
Data Hold Time after Falling Edge of SCLK	t5	10			ns		3
Bus Relinquish Time after Falling Edge of SCLK	t6			50	ns		3
VDD to AGND	VDD	-0.3		7	V	TA = 25°C	4
VDD to DGND	VDD	-0.3		7	V	TA = 25°C	4
Analog Input Voltage to AGND	VIN	-0.3			V	max is VDD + 0.3 V	4
Digital Input Voltage to DGND		-0.3			V	max is VDD + 0.3 V	4
Digital Output Voltage to DGND		-0.3			V	max is VDD + 0.3 V	4
Operating Temperature Range, Industrial (A Version)		-40		85	°C		4
Storage Temperature Range		-65		150	°C		4
Junction Temperature				150	°C		4
SOIC Package Power Dissipation				450	mW	SOIC package	4
Lead Temperature, Vapor Phase (60 sec)				215	°C	SOIC soldering	4
Lead Temperature, Infrared (15 sec)				220	°C	SOIC soldering	4
ESD		4000			V	>4000 V	4
SOIC Thermal Impedance	θJA		160		°C/W	SOIC package	4
SOIC Thermal Impedance	θJC		75		°C/W	SOIC package	4

CAD (KiCad official)

Symbol: AD7896ARZ
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: ad7896arz-etched.step / ad7896arz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7896arz.step / ad7896arz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (15 pp, sha256 e78b0d096aaa5de7, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD7896ARZ

Verified AD7896ARZ

Verification log 1 record

3D Model

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Datasheet

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