component
AD7894ARZ-10
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD7894ARZ-10
Analog Devices · Analog To Digital Converters (ADCs) · SOIC-8
AD7894ARZ-10 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REF IN | input | Voltage reference input, buffered on-chip, to which an external reference of nominal +2.5 V must be connected for correct conversion. |
| 2 | VIN | power_in | Analog input channel whose range is ±10 V for the AD7894-10. |
| 3 | GND | power_in | Analog ground serving as the ground reference for the track/hold, comparator, digital circuitry and DAC. |
| 4 | SCLK | input | External serial clock input that clocks out new data bits on its falling edge, with data valid for 10 ns after that edge, and which should be held low at the end of serial transmission. |
| 5 | SDATA | tri_state | Serial data output providing two leading zeroes followed by 14 bits of two's complement conversion data for the AD7894-10, clocked out on SCLK falling edges and three-stated after the 16th falling edge. |
| 6 | BUSY | output | Conversion status output that goes high on the falling edge of CONVST and returns low when the conversion is complete. |
| 7 | CONVST | input | Edge-triggered conversion start input whose falling edge puts the track/hold into hold and starts conversion, and which powers the part down if low at end of conversion. |
| 8 | VDD | power_in | Positive supply voltage of +5 V ±5%. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Signal to (Noise + Distortion) Ratio @ +25°C | 78 | dB | fIN = 70 kHz Sine Wave, fSAMPLE = 160 kHz | 2 | |||
| Signal to (Noise + Distortion) Ratio, TMIN to TMAX | 77 | dB | TMIN to TMAX; See Figure 14 | 2 | |||
| Total Harmonic Distortion (THD) | -86 | dB | fIN = 10 kHz Sine Wave, fSAMPLE = 160 kHz; Typically -87 dB. See Figure 15 | 2 | |||
| Relative Accuracy | -2 | 2 | LSB | 2 | |||
| Differential Nonlinearity | -1 | 1.5 | LSB | 2 | |||
| Positive Gain Error | -8 | 8 | LSB | AD7894-10, AD7894-3 only | 2 | ||
| Negative Gain Error | -8 | 8 | LSB | AD7894-10, AD7894-3 only | 2 | ||
| Bipolar Zero Error | -10 | 10 | LSB | AD7894-10, AD7894-3 only | 2 | ||
| Analog Input Voltage Range (AD7894-10) | -10 | 10 | V | AD7894-10 | 2 | ||
| Analog Input Current (AD7894-10) | 2 | mA | See Analog Input Section | 2 | |||
| REF IN Input Voltage Range | 2.375 | 2.625 | V | 2.5 V ± 5% | 2 | ||
| REF IN Input Current | 1 | µA | 2 | ||||
| REF IN Input Capacitance | 10 | pF | Sample tested @ +25°C | 2 | |||
| Input High Voltage | VINH | 2.4 | V | VDD = 5 V ± 5% | 2 | ||
| Input Low Voltage | VINL | 0.8 | V | VDD = 5 V ± 5% | 2 | ||
| Input Current | IIN | -10 | 10 | µA | VIN = 0 V to VDD | 2 | |
| Input Capacitance | CIN | 10 | pF | Sample tested @ +25°C | 2 | ||
| Output High Voltage | VOH | 4 | V | ISOURCE = 400 µA | 2 | ||
| Output Low Voltage | VOL | 0.4 | V | ISINK = 1.6 mA | 2 | ||
| Conversion Time, Mode 1 | 5 | µs | Mode 1 Operation | 2 | |||
| Conversion Time, Mode 2 | 10 | µs | Mode 2 Operation; includes wake-up time from standby | 2 | |||
| Track/Hold Acquisition Time | 0.35 | µs | 2 | ||||
| Supply Current | IDD | 5.5 | mA | Digital inputs @ VDD, VDD = 5 V ± 5% | 3 | ||
| Power Dissipation | 20 | 27.5 | mW | Typically 20 mW | 3 | ||
| Power-Down Mode Supply Current | IDD | 20 | µA | TMIN to TMAX; Digital inputs @ GND, VDD = 5 V ± 5% | 3 | ||
| Power-Down Mode Power Dissipation | 15 | 100 | µW | TMIN to TMAX; Typ 15 µW | 3 | ||
| CONVST Pulsewidth | t1 | 40 | ns | CONVST Pulsewidth | 3 | ||
| SCLK High Pulsewidth | t2 | 31.252 | ns | SCLK High Pulsewidth | 3 | ||
| SCLK Low Pulsewidth | t3 | 31.252 | ns | SCLK Low Pulsewidth | 3 | ||
| Data Access Time after Falling Edge of SCLK | t4 | 603 | ns | Data Access Time after Falling Edge of SCLK; VDD = 5 V ± 5% | 3 | ||
| Data Hold Time after Falling Edge of SCLK | t5 | 10 | ns | Data Hold Time after Falling Edge of SCLK | 3 | ||
| Bus Relinquish Time after Falling Edge of SCLK | t6 | 204 | ns | Bus Relinquish Time after Falling Edge of SCLK | 3 | ||
| VDD to GND | VDD | -0.3 | 7 | V | 3 | ||
| Analog Input Voltage to GND (AD7894-10) | -17 | 17 | V | AD7894-10 | 3 | ||
| Reference Input Voltage to GND (printed max VDD + 0.3 V) | -0.3 | V | 3 | ||||
| Digital Input Voltage to GND (printed max VDD + 0.3 V) | -0.3 | V | 3 | ||||
| Digital Output Voltage to GND (printed max VDD + 0.3 V) | -0.3 | V | 3 | ||||
| Operating Temperature Range (Commercial, A, B Versions) | -40 | 85 | °C | Commercial (A, B Versions) | 3 | ||
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| Junction Temperature | 150 | °C | 3 | ||||
| SOIC Package Power Dissipation | 450 | mW | SOIC package | 3 | |||
| θJA Thermal Impedance | θJA | 170 | °C/W | 3 | |||
| Lead Temperature, Soldering, Vapor Phase | 215 | °C | 60 sec | 3 | |||
| Lead Temperature, Soldering, Infrared | 220 | °C | 15 sec | 3 | |||
| Supply Voltage (VDD nominal) | VDD | 5 | V | nom ±5% for Specified Performance | 3 |
CAD (KiCad official)
- Symbol:
AD7894ARZ-10 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ad7894arz-10-etched.step/ad7894arz-10-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7894arz-10.step/ad7894arz-10.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (12 pp, sha256
78b80c261686698b, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD7894ARZ-10
**Analog Devices** · Analog To Digital Converters (ADCs) · SOIC-8
AD7894ARZ-10 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REF IN | input | Voltage reference input, buffered on-chip, to which an external reference of nominal +2.5 V must be connected for correct conversion. |
| 2 | VIN | power_in | Analog input channel whose range is ±10 V for the AD7894-10. |
| 3 | GND | power_in | Analog ground serving as the ground reference for the track/hold, comparator, digital circuitry and DAC. |
| 4 | SCLK | input | External serial clock input that clocks out new data bits on its falling edge, with data valid for 10 ns after that edge, and which should be held low at the end of serial transmission. |
| 5 | SDATA | tri_state | Serial data output providing two leading zeroes followed by 14 bits of two's complement conversion data for the AD7894-10, clocked out on SCLK falling edges and three-stated after the 16th falling edge. |
| 6 | BUSY | output | Conversion status output that goes high on the falling edge of CONVST and returns low when the conversion is complete. |
| 7 | CONVST | input | Edge-triggered conversion start input whose falling edge puts the track/hold into hold and starts conversion, and which powers the part down if low at end of conversion. |
| 8 | VDD | power_in | Positive supply voltage of +5 V ±5%. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Signal to (Noise + Distortion) Ratio @ +25°C | | 78 | | | dB | fIN = 70 kHz Sine Wave, fSAMPLE = 160 kHz | 2 |
| Signal to (Noise + Distortion) Ratio, TMIN to TMAX | | 77 | | | dB | TMIN to TMAX; See Figure 14 | 2 |
| Total Harmonic Distortion (THD) | | | | -86 | dB | fIN = 10 kHz Sine Wave, fSAMPLE = 160 kHz; Typically -87 dB. See Figure 15 | 2 |
| Relative Accuracy | | -2 | | 2 | LSB | | 2 |
| Differential Nonlinearity | | -1 | | 1.5 | LSB | | 2 |
| Positive Gain Error | | -8 | | 8 | LSB | AD7894-10, AD7894-3 only | 2 |
| Negative Gain Error | | -8 | | 8 | LSB | AD7894-10, AD7894-3 only | 2 |
| Bipolar Zero Error | | -10 | | 10 | LSB | AD7894-10, AD7894-3 only | 2 |
| Analog Input Voltage Range (AD7894-10) | | -10 | | 10 | V | AD7894-10 | 2 |
| Analog Input Current (AD7894-10) | | | | 2 | mA | See Analog Input Section | 2 |
| REF IN Input Voltage Range | | 2.375 | | 2.625 | V | 2.5 V ± 5% | 2 |
| REF IN Input Current | | | | 1 | µA | | 2 |
| REF IN Input Capacitance | | | | 10 | pF | Sample tested @ +25°C | 2 |
| Input High Voltage | VINH | 2.4 | | | V | VDD = 5 V ± 5% | 2 |
| Input Low Voltage | VINL | | | 0.8 | V | VDD = 5 V ± 5% | 2 |
| Input Current | IIN | -10 | | 10 | µA | VIN = 0 V to VDD | 2 |
| Input Capacitance | CIN | | | 10 | pF | Sample tested @ +25°C | 2 |
| Output High Voltage | VOH | 4 | | | V | ISOURCE = 400 µA | 2 |
| Output Low Voltage | VOL | | | 0.4 | V | ISINK = 1.6 mA | 2 |
| Conversion Time, Mode 1 | | | | 5 | µs | Mode 1 Operation | 2 |
| Conversion Time, Mode 2 | | | | 10 | µs | Mode 2 Operation; includes wake-up time from standby | 2 |
| Track/Hold Acquisition Time | | | | 0.35 | µs | | 2 |
| Supply Current | IDD | | | 5.5 | mA | Digital inputs @ VDD, VDD = 5 V ± 5% | 3 |
| Power Dissipation | | | 20 | 27.5 | mW | Typically 20 mW | 3 |
| Power-Down Mode Supply Current | IDD | | | 20 | µA | TMIN to TMAX; Digital inputs @ GND, VDD = 5 V ± 5% | 3 |
| Power-Down Mode Power Dissipation | | | 15 | 100 | µW | TMIN to TMAX; Typ 15 µW | 3 |
| CONVST Pulsewidth | t1 | 40 | | | ns | CONVST Pulsewidth | 3 |
| SCLK High Pulsewidth | t2 | 31.252 | | | ns | SCLK High Pulsewidth | 3 |
| SCLK Low Pulsewidth | t3 | 31.252 | | | ns | SCLK Low Pulsewidth | 3 |
| Data Access Time after Falling Edge of SCLK | t4 | | | 603 | ns | Data Access Time after Falling Edge of SCLK; VDD = 5 V ± 5% | 3 |
| Data Hold Time after Falling Edge of SCLK | t5 | 10 | | | ns | Data Hold Time after Falling Edge of SCLK | 3 |
| Bus Relinquish Time after Falling Edge of SCLK | t6 | | | 204 | ns | Bus Relinquish Time after Falling Edge of SCLK | 3 |
| VDD to GND | VDD | -0.3 | | 7 | V | | 3 |
| Analog Input Voltage to GND (AD7894-10) | | -17 | | 17 | V | AD7894-10 | 3 |
| Reference Input Voltage to GND (printed max VDD + 0.3 V) | | -0.3 | | | V | | 3 |
| Digital Input Voltage to GND (printed max VDD + 0.3 V) | | -0.3 | | | V | | 3 |
| Digital Output Voltage to GND (printed max VDD + 0.3 V) | | -0.3 | | | V | | 3 |
| Operating Temperature Range (Commercial, A, B Versions) | | -40 | | 85 | °C | Commercial (A, B Versions) | 3 |
| Storage Temperature Range | | -65 | | 150 | °C | | 3 |
| Junction Temperature | | | | 150 | °C | | 3 |
| SOIC Package Power Dissipation | | | | 450 | mW | SOIC package | 3 |
| θJA Thermal Impedance | θJA | | 170 | | °C/W | | 3 |
| Lead Temperature, Soldering, Vapor Phase | | | | 215 | °C | 60 sec | 3 |
| Lead Temperature, Soldering, Infrared | | | | 220 | °C | 15 sec | 3 |
| Supply Voltage (VDD nominal) | VDD | | 5 | | V | nom ±5% for Specified Performance | 3 |
## CAD (KiCad official)
- Symbol: `AD7894ARZ-10`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ad7894arz-10-etched.step` / `ad7894arz-10-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7894arz-10.step` / `ad7894arz-10.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7894.pdf) (12 pp, sha256 `78b80c261686698b`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad7894arz-10-datasheet.pdf)